By Topic

Solid-State Circuits, IEEE Journal of

Issue 9 • Date Sept. 2009

Filter Results

Displaying Results 1 - 25 of 38
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (49 KB)  
    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2009 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (40 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2009 , Page(s): 2261 - 2262
    Save to Project icon | Request Permissions | PDF file iconPDF (48 KB)  
    Freely Available from IEEE
  • New Associate Editors

    Publication Year: 2009 , Page(s): 2263 - 2264
    Save to Project icon | Request Permissions | PDF file iconPDF (543 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Introduction to the Special Section on the 2008 Bipolar/BiCMOS Circuits and Technology Meeting

    Publication Year: 2009 , Page(s): 2265 - 2266
    Save to Project icon | Request Permissions | PDF file iconPDF (155 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Bipolar Transistor Excess Phase Modeling in Verilog-A

    Publication Year: 2009 , Page(s): 2267 - 2275
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB) |  | HTML iconHTML  

    The collector current Ic of a bipolar transistor does not instantaneously respond to changes in applied base-emitter voltage Vbe ; its response exhibits a time lag because of the finite transit time of carriers through the transistor, which is manifest as a phase lag (or ldquoexcess phaserdquo) in the frequency domain. In this paper we present an excess phase model that has a constant magnitude response, in contrast to previous models which introduce a change in magnitude as well as in phase, and detail how our model can be implemented in Verilog-A. In addition, we show how a bias dependence of the time lag can be added to the Verilog-A implementation of the Weil-McNamee excess phase model without introducing undesired behavior. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Highly Efficient Wideband RF Polar Transmitters Using the Envelope-Tracking Technique

    Publication Year: 2009 , Page(s): 2276 - 2294
    Cited by:  Papers (30)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4785 KB) |  | HTML iconHTML  

    This paper discusses the design issues of highly efficient and monolithic wideband RF polar transmitters, especially the ones that use the envelope-tracking (ET) technique. Besides first reviewing the current state-of-the-art polar transmitters in the literature, three focus topics will be discussed: 1) the system-on-a-chip (SoC) design considerations of the monolithic polar transmitter using ET versus EER (envelope elimination and restoration); 2) the design of highly efficient envelope amplifier capable of achieving the high efficiency, current, bandwidth, accuracy and noise specifications required for wideband signals; and 3) the design of high-efficiency monolithic Si-based class E power amplifiers (PAs) suitable for ET-based RF polar transmitters. A design prototype of a polar transmitter using ET and a monolithic SiGe PA that passed the stringent low-band EDGE (Enhanced Data rates for GSM Evolution) transmit mask with 45% overall transmitter system efficiency will be given; the simulated data of the entire polar transmitter system is also compared against the measurement. Further investigations on how to solve the technical challenges to successfully implement linear and high-efficiency ET-based polar transmitter for broadband wireless applications such as WiBro/WiMAX are also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators

    Publication Year: 2009 , Page(s): 2295 - 2311
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5122 KB) |  | HTML iconHTML  

    The design and wafer probe test results of a 5-bit SiGe flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 0.13 \mu m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

    Publication Year: 2009 , Page(s): 2312 - 2321
    Cited by:  Papers (48)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3115 KB) |  | HTML iconHTML  

    This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and AlN Cooling

    Publication Year: 2009 , Page(s): 2322 - 2338
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3016 KB) |  | HTML iconHTML  

    This paper reviews special RF/microwave silicon device implementations in a process that allows two-sided contacting of the devices: the back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the improved device performance that can be achieved. In particular, high-quality SOG varactors have been developed and an overview is given of a number of innovative highly-linear circuit configurations that have successfully made use of the special device properties. A high flexibility in device design is achieved by two-sided contacting because it eliminates the need for buried layers. This aspect has enabled the implementation of varactors with special Ndx -2 doping profiles and a straightforward integration of complementary bipolar devices. For the latter, the integration of AlN heatspreaders has been essential for achieving effective circuit cooling. Moreover, the use of Schottky collector contacts is highlighted also with respect to the potential benefits for the speed of SiGe heterojunction bipolar transistors (HBTs). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Class-G Supply Modulator and Class-E PA in 130 nm CMOS

    Publication Year: 2009 , Page(s): 2339 - 2347
    Cited by:  Papers (39)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1707 KB) |  | HTML iconHTML  

    A class-G supply modulator utilizes parallel low- dropout (LDO) regulators that are controlled by comparators and negative feedback. It optimizes the power consumption of a nonlinear power amplifier (PA) operating with supply modulation, such that it draws current from one of multiple appropriately sized supply voltages as determined by the input signal envelope. The class-G modulator is used in conjunction with a class-E PA operating in an envelope elimination and restoration (EER) mode to efficiently amplify signals with large peak-to-average ratios. The measured maximum output power and power added efficiency (PAE) are 29.3 dBm and 69%, respectively. The class-G technique is demonstrated for a 64 QAM, OFDM input signal (symbol period = 4 mus) wherein the measured error vector magnitude (EVM) is 2.5% and the average efficiency of 22.6%. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10 MS/s 11-bit 0.19 mm ^{2} Algorithmic ADC With Improved Clocking Scheme

    Publication Year: 2009 , Page(s): 2348 - 2355
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (782 KB) |  | HTML iconHTML  

    A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19 mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13 mum thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10 \sim 15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration

    Publication Year: 2009 , Page(s): 2356 - 2365
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1239 KB) |  | HTML iconHTML  

    Floating-point analog-to-digital converter (FADC) utilizes an up-front variable-gain amplifier (VGA) to enhance its low-level resolution. Although it is a single-path system, varying gain by switching circuit elements in and out modulates the gain and offset as in the multi-path time-interleaved ADC. For high-speed operation at all gain settings, a constant-bandwidth switched-capacitor VGA is implemented with variable-bandwidth opamps, and its gain and offset are digitally calibrated in background using signal-dependent pseudo-random noise (PN) dithering and chopping techniques. A three-stage VGA adjusts its gain instantly from times 1 to times 32 depending on the sampled input level, and improves the INL of a 10-bit ADC from 24 to 0.9 least significant bits (LSBs) at a 15-bit level for the low-level input. The resulting 10 ~ 15-bit 60-MS/s ADC needs no input sample-and-hold (S/H) stage, and achieves a system noise of -80 dBFS with a gain set to times32. A prototype chip in 0.18-mum CMOS occupies an active area of 3.0times2.0 mm2, and consumes 300 mW at 1.8 V including digital calibration logic. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 12-Bit 200-MHz CMOS ADC

    Publication Year: 2009 , Page(s): 2366 - 2380
    Cited by:  Papers (62)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1927 KB) |  | HTML iconHTML  

    A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Fifth-Order G _{\rm m} –C Continuous-Time \Delta \Sigma Modulator With Process-Insensitive Input Linear Range

    Publication Year: 2009 , Page(s): 2381 - 2391
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1747 KB) |  | HTML iconHTML  

    Continuous-time ¿¿ modulators (CT-DSMs) that use transistor-based Gm-C integrators are simple but sensitive to process and temperature variations. Their performance depends heavily on the input linear range that varies widely. A CT-DSM is implemented using a triode Gm-C integrator and a tri-level switched-capacitor digital-to-analog converter (SCDAC). A self-scaling SCDAC keeps the input signal range constant, and an adaptive input common-mode bias control enables the triode Gm cell to operate always with its constant input linear range. The proposed Gm cell exhibits a tuning range of ± 15% while maintaining its linear range over the temperature variation from -30°C to 85°C. A 2-MHz bandwidth, fifth-order CT-DSM in 0.18 ¿m CMOS samples at 128 MS/s with an over-sampling ratio of 32 (OSR = 32), occupies an active area of 0.4 mm2, and consumes 11 mW at 1.8 V. With a -3 dB input of the full scale (400 mV), the measured dynamic range, second harmonic distortion (HD2), and third harmonic distortion (HD3) are 71, -86, and -91 dB, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback

    Publication Year: 2009 , Page(s): 2392 - 2401
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB) |  | HTML iconHTML  

    A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 ¿m CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers

    Publication Year: 2009 , Page(s): 2402 - 2410
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2691 KB) |  | HTML iconHTML  

    The proliferation of portable electronic products such as cellular telephones and personal digital assistants has created a high demand for small format liquid crystal displays (LCD) with increasing bit resolution. The electronic drivers for these display applications must adhere to stringent power and area budgets. This paper describes a low-power, area efficient, scalable, digital-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. A 12 channel, 9-bit DAC driver based on this architecture, implemented in 0.5 mum CMOS technology and suitable for 1/4 VGA resolution displays, exhibited a 2 MSPS conversion rate, 252 muW power dissipation per channel using a 5 V supply, and a per DAC die area of 0.042 mm2. This performance sets a new standard for DAC display drivers in joules per bit areal density at less than 0.58 pJ per bit per mm2 . View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

    Publication Year: 2009 , Page(s): 2411 - 2425
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1731 KB) |  | HTML iconHTML  

    We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular VT devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 V supply while the divider uses a 0.65 V supply. The frequency synthesizer achieves a phase noise better than -120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An FIR-Embedded Noise Filtering Method for \Delta \Sigma Fractional-N PLL Clock Generators

    Publication Year: 2009 , Page(s): 2426 - 2436
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1540 KB) |  | HTML iconHTML  

    This paper describes a noise filtering method for ¿¿ fractional- N PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the ¿¿ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR ¿¿ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz ¿¿ fractional-N PLL is implemented in 0.18 ¿m CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 7 ps Jitter 0.053 mm ^{2} Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC

    Publication Year: 2009 , Page(s): 2437 - 2451
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3659 KB) |  | HTML iconHTML  

    This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 mum CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7 ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Wideband PLL-Based G/FSK Transmitter in 0.18 \mu m CMOS

    Publication Year: 2009 , Page(s): 2452 - 2462
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2447 KB) |  | HTML iconHTML  

    A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed sigma-delta modulated phase rotator (¿¿-PR). By properly combining the multi-phase signals from the PLL output, the ¿¿-PR effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed ¿¿-PR adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the ¿¿-PR on the TX output noise is also analyzed in this paper. The proposed TX with the ¿¿-PR is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 ¿m CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of -11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

    Publication Year: 2009 , Page(s): 2463 - 2477
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1943 KB) |  | HTML iconHTML  

    This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 ¿m CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of -116 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of -122.8 dBc/Hz at 1 MHz offset from a 4.77 GHz carrier. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

    Publication Year: 2009 , Page(s): 2478 - 2487
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2151 KB) |  | HTML iconHTML  

    A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 mm2 active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages

    Publication Year: 2009 , Page(s): 2488 - 2495
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2124 KB) |  | HTML iconHTML  

    A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

    Publication Year: 2009 , Page(s): 2496 - 2502
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (780 KB) |  | HTML iconHTML  

    This paper describes a reconfigurable analog baseband (ABB) for a software-defined radio (SDR). A wide variety of filter characteristics needed for SDR can be obtained by a reconfigurable filter based on a newly developed duty-cycle controlled discrete-time transconductor. The ABB, implemented in a 90 nm CMOS process, provides second- and fourth-order Butterworth, Chebyshev, and elliptic responses with bandwidths from 400 kHz to 30 MHz. The chip draws only 12 mA and achieves a P1dB of +7 dBm with a 1.0 V supply. The input-referred integrated in-band noise is 0.31 mVrms and the die area is as small as 0.57 mm2. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan