By Topic

Electronic Computers, IRE Transactions on

Issue 1 • Date March 1957

Filter Results

Displaying Results 1 - 18 of 18
  • [Front cover]

    Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (555 KB)  
    Freely Available from IEEE
  • IRE Professional Group on Electronic Computers

    Page(s): nil1
    Save to Project icon | Request Permissions | PDF file iconPDF (99 KB)  
    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
    Save to Project icon | Request Permissions | PDF file iconPDF (99 KB)  
    Freely Available from IEEE
  • The Logic of Bidirectional Binary Counters

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    The counters without short-time internal memory, conceived by Bigelow, disclosed by Ware, and extended by Brown, are discussed from the standpoint of their respective logic. It is shown that the (self-instructed) bidirectional1 counter of Brown has a more rigorous logic than the unidirectional counter of Ware; the operation of Brown's bidirectional counter being subjected to the only restriction that its speed be compatible with the operating speed of its individual toggles, whereas the operation of Ware's counter is predicated upon the existence of unspecified buffering states in the input of each stage, to prevent run-away conditions. These buffering states, which occur naturally in Brown's bidirectional counter, can be provided explicitly in unidirectional counters by replacing the two transfer circuits of Ware's counter stage, which are controlled only by one toggle of the preceding stage, by two of the four transfer circuits of Brown's bidirectional counter stage, all four of which are controlled by both toggles of the preceding stage. This paper introduces the viewpoint that a bidirectional counter of Brown's type is a counter in which the state of one toggle of each stage determines which toggle of the next stage is master, while the state of the other toggle of each stage determines whether the slave of the next stage shall be like or unlike the master. This viewpoint permits a succinct discussion of the several possible interstage connections, and of the several counting codes obtained for each connection. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Logical Design of a Simple General Purpose Computer

    Page(s): 5 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2002 KB)  

    The logical design described here is used in MINAC, partially constructed at the California Institute of Technology, and LGP-30, manufactured by Librascope Inc. These serial binary digital computers make use of magnetic drum bulk storage and use three circulating registers and fifteen flip-flops. The procedures used in performing the sixteen elementary operations are described. These descriptions indicate the circumstances in which each flip-flop or circulating register input is activated. The Boolean algebraic equations summarizing these circumstances constitute the logical design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Transistor-Driven Magnetic-Core Memory

    Page(s): 14 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2872 KB)  

    A transistor-driven magnetic-core memory which has a capacity of 1024 18-bit words has been built and is being studied. Both the read and write operations employ the coincident-current technique. The memory-drive currents are developed by transistors and the desired memory location is selected by magnetic-core selection switches. Eighteen thousand, four hundred and thirty-two memory cores are used in the storage array, 48 switching cores are used in the selection switches, and 160 transistors are used in core-driving circuits and read-out amplifiers. A typical memory cycle, reading followed immediately by writing, requires 20 microseconds. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Current Steering in Magnetic Circuits

    Page(s): 21 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2862 KB)  

    Magnetic switches are described in which the current from an energizing source is guided or steered through one out of many possible parallel branches, the conducting branch being selected by the presetting of appropriate magnetic elements. Only a few tubes are required for energization, and the outputs, obtained with reasonable efficiency, are substantially independent of exact circuit parameters. Current steering is achieved either by core-diode combinations or by transfluxors. Decoding switches, of both types, for the selection of one out-of-many outputs according to an input code are described in detail. A current of precise amplitude of the order of amperes is switched to a selected path in microseconds. Steered decoders are ideal for addressing core memories. A commutator switch for delivering sequentially a given current to a number of loads is described. Current steering makes possible simple magnetic counters and universal code converters. Experimental results of laboratory models of decoders and commutators are given. The principle of current steering broadens greatly the usefulness of magnetic switches by providing economy of associated electronic drivers and accuracy of switched currents. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Electronic Analog Multiplier Using Carriers

    Page(s): 30 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1356 KB)  

    An electronic analog multiplier is described, which is based on a modulation technique. No dc amplifiers are used, which makes the output entirely free of drifts. All distortions up to the fourth order are eliminated. The experimental model that has been built handles inputs from dc to 7 kc and gives an output from dc to 14 kc. The amplitude range of the output is 50 db. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ways of Developing Soviet Computer Production

    Page(s): 37 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3691 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PGEC Membership Survey

    Page(s): 49 - 55
    Save to Project icon | Request Permissions | PDF file iconPDF (921 KB)  
    Freely Available from IEEE
  • Review of Electronic Computer Progress During 1956

    Page(s): 55 - 60
    Save to Project icon | Request Permissions | PDF file iconPDF (1585 KB)  
    Freely Available from IEEE
  • Contributors

    Page(s): 60 - 61
    Save to Project icon | Request Permissions | PDF file iconPDF (385 KB)  
    Freely Available from IEEE
  • PGEC News

    Page(s): 61 - 62
    Save to Project icon | Request Permissions | PDF file iconPDF (331 KB)  
    Freely Available from IEEE
  • Reviews of Current Literature

    Page(s): 63 - 69
    Save to Project icon | Request Permissions | PDF file iconPDF (1131 KB)  
    Freely Available from IEEE

Aims & Scope

This Transactions ceased publication in 1962. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope