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Electronic Computers, IRE Transactions on

Issue 4 • Date Dec. 1960

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Displaying Results 1 - 25 of 32
  • [Front cover]

    Page(s): c1
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  • IRE Professional Group on Electronic Computers

    Page(s): nil1
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  • [Breaker page]

    Page(s): nil1
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  • Improvements to Current Switching

    Page(s): 415 - 418
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    Diode switching circuits have been used in conjunction with emitter followers and current switching circuits to evolve a new set of system building blocks. These blocks exhibit typical delays under five millimicroseconds. Diodes cost less and are physically smaller than transistors; therefore, this new system is cheaper and faster than an all-current switching system and permits at least a fivefold increase in packaging density. View full abstract»

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  • System Application of Hybrid Logic Circuitry

    Page(s): 418 - 423
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    A comparative performance rating of circuit techniques for performing logical functions in digital systems may be based upon: 1) Reliability and simplicity 2) Input and output capabilities 3) Propagation time 4) Cost. The ``Hybrid Transistor Diode Logic'' (HTDL) circuit technique employs either diodes or emitter follower transistors as gates and buffers, to maximize the circuit performance rating. The HTDL technique thus combines the advantages of lumped and distributed gain circuits. The cascading of diodes and emitter followers in logical gate matrices can be analyzed as the transmission of binary signals through a video system of a given bandwidth. The HTDL technique optimizes the use of the transistor through nonsaturating, low-impedance circuitry. This optimum use of 200-500 megacycle gain-bandwidth transistors is primarily limited by present-day packaging techniques and their inductive and capacitive loading effects upon the circuits. The development of macromodule packaging techniques, using 200-500 mc transistors, in HTDL circuitry, would permit system speeds (synchronous clock rates) to exceed 50 Mc. View full abstract»

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  • Esaki Diode Logic Circuits

    Page(s): 423 - 429
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    The Esaki diode is a potentially low-cost, high-speed two-terminal device exhibiting a short-circuit-stable negative resistance over a portion of its volt-ampere characteristic. By proper biasing and loading, it can be used to perform power amplification and memory functions. In this paper, a variety of digital computer circuits (a result of an early exploratory program) is described which utilizes the above properties. In particular, shift registers, triggers, and counters are presented. The following shift registers are described: 1) A register which consists of one Esaki diode and one conventional diode per stage. Shifting is accomplished with a two-phase square-wave drive. The Esaki diode provides memory and power gain, and the conventional diode provides a unilateral flow of information. 2) A register which combines Esaki diodes with square-loop ferromagnetic cores. Again the Esaki diode provides memory and power gain. Upon application of a single-phase drive, the cores perform a gating operation depending upon the state of the diodes. 3) With the use of Esaki diode-transistor combinations, high-speed circuits are obtained which depend upon the Esaki diodes primarily for memory and the transistors for power gain and unilateral flow of information. The flip-flop and counter circuits to be presented are the following: 1) A binary counter using Esaki diodes with magnetic cores; 2) high-speed flipflops using Esaki diode-transistor combinations. View full abstract»

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  • Tunnel Diode Logic Circuits

    Page(s): 430 - 438
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    The recent discovery of the tunnel diode with band-widths extending into the kilomegacycle region has prompted investigation of their use in the logic and control portions of high-speed computers. Considerations of diode uniformity requirements, stability problems and power supply requirements has led to a monostable type of logical circuit. The switching properties of this circuit are analyzed and found to depend upon the negative resistance¿capacitance time constant of the unit. The basic function performed by the circuit is a thresholding operation from which a set of logical building blocks is derived. Compatible dynamic and bistable storage schemes are discussed. Of major importance is the effect of diode variations upon the logical gains and delays of the circuits. These properties have been tabulated for tunnel diodes with 5 per cent tolerances on knee current and voltage. Experimental circuits using diodes with a time constant of 1.4 nanoseconds have given a nominal switching time of 7.5 nanoseconds. View full abstract»

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  • A Secondary-Emission Pulse Circuit, Its Analysis and Application

    Page(s): 439 - 451
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    This paper describes a regenerative pulse circuit using a single secondary-emission tube that is able to generate pulses having a rise time of 6 m¿sec and a width continuously variable from 25 m¿sec to 12 ¿sec. First, a theoretical discussion of the circuit is given in which expressions for pulse width and rise time are derived. Then, various practical realizations of the circuit are presented. Among others, these include a millimicrosecond pulse generator and a fast pulse height discriminator. View full abstract»

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  • An Electrically Alterable Nondestructive Twistor Memory

    Page(s): 451 - 455
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    The twistor is a relatively new memory device which may be operated either in a conventional destructive read-out mode, or, by the method explained in this paper, in a nondestructive mode. This paper discusses the basic principles of twistor operation and shows how the twistor may be fabricated into a memory. A non-destructive method of reading a twistor memory by the use of multiple solenoids is described. A typical configuration of a twistor memory which, by the use of this nondestructive reading method, may be operated either in a destructive mode or in a nondestructive mode, is shown. View full abstract»

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  • Current Build-Up in Avalanche Transistors with Resistance Loads

    Page(s): 456 - 460
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    A transient analysis for the avalanche transistor is carried out through the use of a diffusion model described in terms of charge variables. Basically, the current as a function of time is calculated by taking the gradient of the minority carrier charge stored in the base region. Two methods of approximating the distribution of stored charge are described. Good agreement has been obtained between calculated and experimental results; it is found that the rise time for the resistance-load case is about four times that for a capacitance-load case which produces the same peak current. A practical pulse generator circuit is described in which the resistance load takes the form of a delay-line. The performance of this circuit is compared with that of a capacitance-load relaxation oscillator; while the rise time of the former is longer, the pulse shape is more easily controlled. View full abstract»

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  • High-Speed Transistorized Adder for a Digital Computer

    Page(s): 461 - 464
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    An adder is described that has been developed for the Floating Indexed Point Arithmetic Unit, FLIP, to be used in conjunction with GEORGE, the existing computer built at Argonne National Laboratory. The logic of the high-speed adder and the special circuits required are presented. The adder is parallel and its high speed is made possible by reducing the carry propagation time. Each bit of the adder contributes one transistor to make up a tall AND gate which reduces the carry propagation time to 0.2 ¿sec. Using this high-speed carry propagation and rather common RCTL transistor circuitry, it is possible to complete an addition in less than 0.25 ¿sec. View full abstract»

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  • Fast High-Accuracy Binary Parallel Addition

    Page(s): 465 - 469
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    Future designs of parallel digital computers will be concerned with increased accuracy in arithmetic operations. When the number of bits per operand is increased, one basic speed limitation to these operations is the time required to propagate carries in addition or borrows in subtraction. A quantitative method of evaluating the drastic reduction in time achieved by asynchronous addition techniques is described. View full abstract»

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  • Characterizing Experiments for Finite-Memory Binary Automata

    Page(s): 469 - 471
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    The characteristics of a discrete automaton with a finite memory can be determined by an experiment of a finite length. This paper discusses the properties of such experiments, and presents methods for their optimal construction. Specific results are given for binary-input automata with the memory ranges 0, 1, 2, 3 and 4. View full abstract»

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  • Statistical Recognition Functions and the Design of Pattern Recognizers

    Page(s): 472 - 477
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    According to the model discussed in this paper, a pattern recognizer is said to consist of two parts: a receptor, which generates a set of measurements of the physical sample to be recognized, and a categorizer, which assigns each set of measurements to one of a finite number of categories. The rule of operation of the categorizer is called the ``recognition function.'' The optimization of the recognition function is discussed, and the form of the optimal function is derived. In practice, a prohibitively large sample is required to provide a basis for estimating the optimal recognition function. If, however, certain assumptions about the probability distributions of the measurements are warranted, recognition functions that are asymptotically optimal may be obtained readily. A small numerical example, involving the recognition of the hand-printed characters A, B, and C is solved by means of the techiques described. The recognition accuracy is found to be 95 per cent. View full abstract»

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  • The Simplification of Multiple-Output Switching Networks Composed of Unilateral Devices

    Page(s): 477 - 486
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    The purpose of this paper is to show that two-level (no more than two gates in cascade) multiple-output switching networks composed of unilateral switching devices such as diodes can be simplified or minimized in much the same manner as single-output networks. This is accomplished by extending the notation and techniques used in the simplification of two-level single-output switching networks to multiple-output switching networks. A simple procedure for identifying multiple-output prime implicants is devised and, as a final result, an algorithm is presented which can be used to minimize the switching network corresponding, to a number (q) of given Boolean expressions of the same variables. This algorithm is based on the Quine rules but has been modified to take advantage of the so-called ``don't care'' conditions which occur because some inputs are forbidden or because some outputs are of no concern. This algorithm can readily be programmed on a digital computer if desired. View full abstract»

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  • Uniqueness of Weighted Code Representations

    Page(s): 487 - 489
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    Decimal computers ordinarily use a binary-coded decimal representation. One class of binary-coded decimal digits is the so-called four-bit weighted code representation with weights ¿1 ¿2 ¿3 ¿4. Each ¿i is a nonzero integer in the range ¿9¿¿i¿9, and the set of weights must have the property that every decimal digit can be represented by the sum ¿i=14 bi ¿i, with the bi being 0 or 1. For some weighted codes the weights are such that some digits can be represented by more than one sum of the specified form. For example, the 7421 weighted code has the property that 7 may be represented either as 1000 or as 0111. This paper produces a necessary and sufficient condition on the weights of a weighted code for the unique representation of each digit by a sum of the specified form. Further, all possible sets of weights are displayed. View full abstract»

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  • Analog Representation of Poisson's Equation in Two Dimensions

    Page(s): 490 - 496
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    A new analog device, called a Poisson cell, has been developed which aids in obtaining solutions to either Laplace's equation or Poisson's equation. The cell may be used to simulate such potentials as electric potential, magnetic potential, gravitational potential, and the velocity potential of irrotational flow; it has applications in the fields of hydrodynamics, heat conduction, and aerodynamics. The cell is a solid volume-conducting medium made from a homogeneous mixture of hydrostone and graphite. Electrode configurations may be painted on the surface with conducting paint or imbedded directly in the structure. In the case of Poisson's equation, where ¿2¿(x, y) = f(x, y), the function f(x, y) is simulated by injecting currents into the underside of the cell. The application of the Poisson cell to numerous problems and in particular to problems in electron flow is discussed m detail, along with the incorporation of the cell into either an analog computer system or a combined analog-digital computer system. View full abstract»

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  • A New, Solid-State, Nonlinear Analog Component

    Page(s): 496 - 503
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    Since the inception of the electronic analog computer as a useful engineering tool, the need for practical methods of solving nonlinear problems has steadily increased. This paper describes a passive, nonlinear device which, when used with operational amplifiers, provides the means for obtaining a large class of functions. These are obtained to a degree of accuracy and reliability not previously possible with a simple, economical device. A basic varistor squaring unit is described. The unit has been compensated for the various types of error inherent in the varistor itself, and is capable of providing approximately fifteen of the most basic and commonly used nonlinear functions. View full abstract»

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  • Solving Integral Equations on a Repetitive Differential Analyzer

    Page(s): 503 - 506
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    Methods of practical solution of integral equations on electronic differential analyzers are not well developed. In those cases where such methods have been outlined, special and costly additional equipment is required. Results presented in this work show that practical solution of integral equations is possible using a repetitive differential analyzer of convenient design. View full abstract»

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  • A New Technique for Analog Integration and Differentiation

    Page(s): 507 - 509
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    A technique is described which enables an approach to ideal analog integration or differentiation by means of passive elements only. A series of RC circuits in a cascade arrangement, uncoupled to each other, provides the first, second, third, etc., integrals or derivatives (according to the connection of the RC circuits) of the input function. The theory establishes that if the outputs of each are fed to an analog summing amplifier, its output becomes arbitrarily close to the ideal integral or derivative of the input function as the number of RC stages is raised indefinitely. A device has been developed according to this idea to perform one of these operations (integration) and to check the results obtained in theory. Mathematical proofs of the theory are given in the paper. View full abstract»

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  • Correction

    Page(s): 509
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  • Contributors

    Page(s): 511 - 514
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  • Reviews of Books and Papers in the Computer Field

    Page(s): 515 - 530
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Aims & Scope

This Transactions ceased publication in 1962. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope