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Electronic Computers, IRE Transactions on

Issue 2 • Date June 1960

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Displaying Results 1 - 25 of 33
  • [Front cover]

    Page(s): c1
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  • IRE Professional Group on Electronic Computers

    Page(s): nil1
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  • [Breaker page]

    Page(s): nil1
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  • Sequence Detection Using All-Magnetic Circuits

    Page(s): 155 - 160
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    A technique is described for detecting specific sequences of pulses occurring on a net of input lines. This technique lends itself to realization in all-magnetic networks by the use of multi-aperture magnetic devices (MAD's). The resulting circuits are remarkably simple and reliable. Processing rates in excess of 100,000 characters per second may be achieved. Examples are given of systems using arrays of such detectors. One example involves a system for detecting handwritten characters which makes use of a special pen having the property of generating specific sequences of pulses as symbols are written. The second example relates to the problem of monitoring text for the detection of specific words (letter sequences) and phrases (series of sequences). View full abstract»

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  • Comparison of Saturated and Nonsaturated Switching Circuit Techniques

    Page(s): 161 - 175
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    The concept that the junction transistor is a charge-controlled current source is reviewed. Saturated operation and non-saturated operation are defined on the basis of minority and majority carrier distributions in the base region. Several common emitter switching circuits are analyzed. The switching efficiency, a figure of merit based on the charge storage properties of the transistor, is introduced. Saturated and nonsaturated operation are compared on the basis of switching efficiency, transient waveforms, stability of the voltage levels, power dissipation, noise rejection and suppression ablity, and circuit complexity. Currently-used antisaturation techniques are discussed. View full abstract»

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  • A New Core Switch for Magnetic Matrix Stores and Other Purposes

    Page(s): 176 - 191
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    This paper analyzes the conventional uses of magnetic switch cores to drive matrix stores in both current-driven and voltage-driven modes. A new method of using switch cores is proposed and analyzed which offers, at the cost of replacing in every selection line the usual switch-core and terminating resistor by two smaller cores, intrinsic pulse shaping and amplitude regulation, and much reduced power dissipation, particularly in the driving stages. Constructional details of an application of the new method to drive a store 100×80×10 are given, and waveforms for this store are shown. All address decoding and driving are performed by 34 transistors. A model of a multiple coincidence store 101×101 with a cycle time of 1 ¿sec has also been constructed; details are given. View full abstract»

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  • Submicrosecond Core Memories Using Multiple Coincidence

    Page(s): 192 - 198
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    Memories using toroidal ferrite cores with cycle timies less than a microsecond are described; the selection ratio is increased by the use of biasing and the multiple coincidence principles of Minnick and Ashenhurst.1 It is shown that this mode of operation leads to important changes in the structure of the store; in particular, the classical core switch does not fulfll the new requirements. The ``two-core switch'' is then briefly described; it permits an elegant and economic solution of the problems arising at high selection ratios. Details of the design and operation of memories embodying these ideas are given; it is shown, for example, that standard core memory matrices can be used very efficiently at a selection ratio of 3:1 to achieve a cycle time of 2 microseconds. Further illustrations are given from a model of a 100×100 store operated at 4:1 and 7:1 selection ratios, and it is shown that a store of 10,000 8-bit characters with a cycle time of 0.25 microsecond is feasible. View full abstract»

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  • Magnetic Fields of Twistors Represented by Confocal Hollow Prolate Spheroids

    Page(s): 199 - 207
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    A twistor is an anisotropic ferromagnetic cylindrical wire with nonmagnetic core. The intrinsic magnetization flux curls in helical sense in the wire and has an air return path. Many field problems must be solved for their successful use as information storage elements. For instance, the demagnetizing field in the wire causes instability of storage and therefore must be reduced by suitable geometry of the twistor. The flux lines emanating from a bit link neighboring windings and also impose a magnetic field intensity in neighboring bits. The interactions, although undesirable in packing bits in a memory array, can be used to advantage as operating forces in logical devices.1 This paper analyzes the demagnetizing field in a twistor bit, based on the geometrical model of a confocal hollow prolate spheroid and the magnetic characterization of the material by B¿ = ¿0(H+M) where M¿ is the intrinsic magnetization, constant in magnitude, but oriented by the external field. Demagnetizing factors for confocal hollow prolate spheroids are plotted against length-to-diameter ratio and wall thickness. Expressions for field intensities outside a twistor bit are given. Analogies between twistors and thin films are examined. View full abstract»

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  • The Design of a General-Purpose Microprogam-Controlled Computer with Elementary Structure

    Page(s): 208 - 213
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    This paper presents the design of a parallel digital computer utilizing a 20-¿sec core memory and a diode storage microprogram unit. The machine is intended as an on-line controller and is organized for ease of maintenance. A word length of 19 bits provides 31 orders referring to memory locations. Fourteen bits are used for addressing, 12 for base address, one for index control, and one for indirect addressing. A 32nd order permits the address bits to be decoded to generate special functions which require no address. The logic of the machine is resistor-transistor; the arithmetic unit is a bus structure which permits many variants of order structure. In order to make logical decisions, a ``general-purpose'' logic unit has been incorporated so that the microcoder has as much freedom in this area as in the arithmetic unit. View full abstract»

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  • An Evaluation of Several Two-Summand Binary Adders

    Page(s): 213 - 226
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    Five fairly representative members of the class of two-summand binary adders are described and evaluated. Hopefully, this will help the development of more general approaches to computer subsystems evaluation. The adders are evaluated on the basis of three quantities: the number of two-input AND gates and OR gates, G; the gate-normalized addition time, ¿; and the number of bits, n, in each summand. Three plausible formulas for computational efficiency, ¿, are postulated, and plotted vs n for the five adders. Based on a comparison of the resulting curves, the following efficiency formula seems preferable: ¿ = n/¿log2G. Of the five adders considered, the new ``conditional-sum adder'' is best by the above formula when n¿ 3. Other adders, however, are shown to be superior when the assumptions underlying the evaluation of G and ¿ are changed. The evaluation is found to have several limitations; these are discussed. Curves of G and ¿ vs n are given. It is suggested that these curves can serve as raw data for other evaluations, so that various evaluation methods may be compared. View full abstract»

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  • Conditional-Sum Addition Logic

    Page(s): 226 - 231
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    Conditional-sum addition is a new mechanism for parallel, high-speed addition of digitally-represented numbers. Its design is based on the computation of ``conditional'' sums and carries that result from the assumption of all the possible distributions of carries for various groups of columns. A rapid-sequence mode of operation provides an addition rate that is invariant with the lengths of the summands. Another advantage is the possibility of realizing the adder with ``integrated devices'' or ``modules.'' The logic of conditional-sum addition is applicable to all positive radices, as well as to multisummand operation. In a companion paper, a comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed. View full abstract»

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  • Constant-Weight Counters and Decoding Trees

    Page(s): 231 - 244
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    A class of counters is described in which the number of 1's in the flip-flops or register stages composing the counter remains constant as the counter advances from state to state. Simple digital circuit arrangements are described for the design of such counters, which may be used with a particular type of decoding tree as economical ring-type counters, to provide a separate output lead for each state. Some interesting theoretical questions concerning the minimization of these decoding trees are raised and partially answered. Finally, the costs of these counters are compared with one another, and with those of other types of counters, over a continuous range of values of the flip-flop/gate-input cost ratio. View full abstract»

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  • Determination of the Irredundant Normal Forms of a Truth Function by Iterated Consensus of the Prime Implicants

    Page(s): 245 - 252
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    This paper describes a new algebraic way of determining irredundant forms from the prime implicants. The method does not require using the developed normal form, and it makes novel application of Quine's technique of iterative consensus-taking. Thus, by applying repeatedly the rule of consensus to the prime implicants, it is possible to derive alist of implication relations that express the necessary and sufficient conditions of eliminability of the prime implicants in terms of which the irredundant normal forms can be computed. The extension of Quine's technique to this phase of simplification serves to shorten considerably the logical machinery needed for complete solution of the simplification problem. By the same token, it renders the method suitable for use with a digital computer. View full abstract»

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  • A Precision Amplitude-Distribution Amplifier

    Page(s): 252 - 255
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    A new electronic slicer circuit produces output pulses whenever a random input voltage x(t) is between two slicing levels X - ¿x/2 and X+¿x/2. The slicer pulses gate a counter to produce a direct digital readout count equal to the estimated first-order probability density of the input signal. The system was designed for random process studies with conventional electronic analog computers and has compatible accuracy. View full abstract»

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  • A Pulse Position Modulation Analog Computer

    Page(s): 256 - 261
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    An important field of application for computers is in real-time systems simulation. This requires the generation of non-linear functions, obtaining the sums and products of these functions and solving systems of nonlinear differential equations. A new type of analog computer suitable for systems simulation is described which combines the desirable features of the digital and analog computers in its mode of operation. Variables are represented by the time interval between pulses. Utilizing a few basic components, it is possible to carry out the operations of addition, subtraction, multiplication and function generation to 0.1 per cent accuracy. View full abstract»

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  • Correction

    Page(s): 261
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  • Progress Toward Block Diagram Standards

    Page(s): 266 - 267
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    First Page of the Article
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  • Contributors

    Page(s): 267 - 269
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    Freely Available from IEEE

Aims & Scope

This Transactions ceased publication in 1962. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope