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Electronic Computers, IRE Transactions on

Issue 4 • Date Dec. 1961

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Displaying Results 1 - 25 of 42
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IRE Professional Group on Electronic Computers

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
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    Freely Available from IEEE
  • The Cascade Decomposition of Sequential Machines

    Page(s): 587 - 592
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    This paper studies composite sequential machines obtained from smaller component machines by their connection in cascade, that is, the outputs from one component are the inputs to the next. Given the specification of a deterministic, completely specified, synchronous, sequential machine (Mealy model), a criterion is derived for such a specification to be decomposable into specifications of smaller machines, the cascading of which will lead to a realization of the original machine required. A simple technique, based on homomorphisms between directed graphs, is arrived at for the actual breaking up of a decomposable specification. A number of additional problems related to sequential machine decompositions are pointed out as concluding remarks. View full abstract»

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  • On the State Assignment Problem for Sequential Machines II

    Page(s): 593 - 603
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    The object of this paper is to find state assignments for the internal states of a sequential machine such that the logical equations representing the machine are relatively simple. This is done by finding assignments for which the computation of a particular state variable depends only on the previous values of a small subset of the variables. The chief tool is the concept of a partition pair, which describes (loosely speaking) the information going into and resulting from the evaluation of a state variable. A necessary and sufficient condition for the existence of assignments with reduced dependence is found in terms of these pairs, and their algebraic properties are worked out so that they can be handled and generated. It is shown that the same methods can also be used to find input and output assignments with reduced dependence. The case of ``don't care'' conditions is considered and the theory is seen to apply, except that the failure of an algebraic property makes it weaker. View full abstract»

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  • A Truth Table Method for the Synthesis of Combinational Logic

    Page(s): 604 - 615
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    This paper describes a method for synthesizing a switching function directly from its: ruth table. A switching function is defined as any mapping of a set of binary input combinations onto 0 and 1. Hence, the procedures apply equally well to the don't care cases. The method rests on the concept alogically passive function (LPF). Roughly speaking, an LPF is a truth table which can be realized with only AND and OR gates¿no inverters. Techniques are described for 1) making a function logically passive, 2) eliminating rows and columns from the truth table of an LPF, 3) synthesizing an LPF in a two-level irredundant form, 4) expanding LPF's and 5) synthesizing LPF's with 3-input majority gates. The underlying methods are quite straightforward and appear to be particularly well suited for mechanization on a digital computer. View full abstract»

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  • The Use of the Simplex Algorithm in the Mechanization of Boolean Switching Functions by Means of Magnetic Cores

    Page(s): 615 - 622
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    An algorithm is described for mechanizing Boolean switching functions by means of a net of magnetic toroidal cores. The algorithm is referred to as Simplex and, in this application, is programmed for a digital computer. Computer solutions specify the wiring configuration for a core or net of cores yielding a device for performing combinational logic. Switching functions are realizable in essentially one clock time. The logical designer may synthesize a function directly from the truth table without proceeding in the customary manner of expressing the function in Boolean canonical form and then attempting to minimize with respect to hardware or other criteria by means of algebraic manipulation or a mapping or charting technique. View full abstract»

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  • An Algorithm for Automatic Design of Logical Cryogenic Circuits

    Page(s): 623 - 630
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    Logical cryogenic circuits differ from the circuitry used with other devices as paths for both the required function and its denial must be provided. Present techniques for logical design of cryogenic circuits either rely on the experience of the designer to achieve a minimal circuit or are derived from analogous relay circuits. An algorithm to develop minimal (or near minimal) circuits by collapsing a complete decoding-tree structure by removing un-needed devices is discussed. The algorithm requires no subjective decisions and is readily programed for inclusion in an automatic design system. A generalization of the algorithm to include functions of n-ary input variables and multiple outputs is also presented. View full abstract»

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  • Geometric Mapping of Switching Functions

    Page(s): 631 - 637
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    The geometric map described in this paper is a graphic representation, using vectors, of the conditions desired in the design of switching networks. This mapping technique makes the well-known techniques such as Boolean algebra, the Quine-McCluskey minimization chart, and Huffman's flow table more effective when designing optimum circuits. Its degree of flexibility in the selection of vectors is advantageous in certain problems. View full abstract»

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  • Bibliography on Switching Circuits and Logical Algebra

    Page(s): 638 - 661
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    This bibliography, which covers material published through 1958, contains nearly 700 references to articles, books, seminars, and other bibliographies pertaining to the theory of switching circuits and logical algebra. A relatively large number of the references are to foreign works, of which the Russian contribution is by far the greatest. An effort has been made to give exact bibliographical references; wherever possible, the titles of the foreign items have been listed in their original language, together with an English translation. Appended to the chronological bibliography are a list of books, a list of other bibliographies, an author index, a subject index, a list of periodicals, and a list of frequently used Russian abbreviations. View full abstract»

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  • An Algorithm for Rapid Binary Division

    Page(s): 662 - 670
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    A new algorithm is given for reducing the number of additions and subtractions required in binary division in a computer. The algorithm is presented in two parts. A simplified algorithm, which can significantly reduce the number of operations with minimal additional circuitry, is used to develop the justification of the method. The complete algorithm introduces modifications which allow the minimum number of operations by examination of no more than the leading five bits of the divisor and remainder. An average of two-thirds can be saved in the number of operations. View full abstract»

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  • A General Junction-Transistor Equivalent Circuit for Use in Large-Signal Switching Analysis

    Page(s): 670 - 679
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    This paper describes a general medium-speed junction-transistor equivalent circuit that is valid for large- and small-signal operation. Solutions of nonlinear differential equations written from the equivalent circuit for its response to large-signal driving pulses are obtained by graphical, analytic, and analog computer techniques. The static base-to-emitter V-I characteristic is used extensively in the various analysis techniques and produces the proper response to a driving source of any internal resistance. In Section II a charge-control equation is employed for constructing the equivalent circuit in a common-emitter hybrid ¿ configuration. Section III deals with the techniques for solving large-signal switching problems. Section IV discusses some of the required measurements. View full abstract»

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  • Using Digital Computers in the Design and Maintenance of New Computers

    Page(s): 680 - 690
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    To conserve manpower and reduce the time needed for designing, assembling, and maintaining new large-scale computers, existing computers have been used to produce design and maintenance data for the new machines automatically. This paper describes some techniques that were devised at the National Bureau of Standards for automatically converting a logical design into detailed wiring plans which specify the actual pin-to-pin connections and other data necessary for assembling, debugging, and maintaining a new machine. Starting from punched-card input transcriptions of the logical design of the new computer, expressed in terms of Boolean algebra, an IBM 704 was programmed to produce 20,000 printed pages of wiring plans, fabrication data, and logical debugging and maintenance manuals. View full abstract»

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  • Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units

    Page(s): 691 - 698
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    After a very brief summary of the various well-known methods of expediting carry-propagation in binary arithmetic units, the paper discusses and develops the ``anticipated-carry'' or ``carry-skip'' technique originally due in decimal form to Babbage, much used in mechanical calculators and lately revived for use in binary units. Various degrees of refinement are possible. It appears that for a given expenditure, the technique results in a unit which is simpler and faster than those using one of the other techniques. Conversely in order to attain a given speed with given circuit elements, the skip technique appears to minimize the equipment requirement among the known speed-up techniques. View full abstract»

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  • Some Properties of Binary Counters with Feedback

    Page(s): 699 - 701
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    Properties of binary counters which have feedback connections are discussed. Various methods of determining the cyclic period have been reported, as well as techniques for synthesizing feedback connections to obtain a specific period. This paper presents a somewhat different approach to the period determination. It also includes a discussion of a simple method for determining the numerical values eliminated from the normal counting sequence by feedback connections. Several illustrative examples are given. View full abstract»

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  • A Magnetostrictive Delay-Line Shift Register

    Page(s): 702 - 708
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    A brief theory of correlation, as applied to the recognition of a specific pattern in a binary signal, is presented. The digital shift register, which lends itself well to the practical application of the theory of correlation, is discussed. By digitizing the binary input signal and applying it to a closed-loop delay line, a time-compressed version of the input signal circulates on the line, and the delay line can perform the same function as the digital shift register, with possible advantages of size and cost over the shift register. Sample parameters are postulated for a shift register, and a shift register employing a magnetostrictive delay line is designed. The operation of the designed delay line shift register is then discussed in detail. View full abstract»

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  • Proposal for Magnetic Domain-Wall Storage and Logic

    Page(s): 708 - 711
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    Magnetic storage of binary digital information is currently accomplished by utilizing the two stable and degenerate energy states corresponding to opposite spatial directions of a magnetic domain. However, a second type of magnetic-energy degeneracy exists since a domain wall separating two domains has the same energy regardless of the sense (clockwise or counter-clockwise) of rotation of the magnetization M within the wall. Hence, the rotational sense of M in passing through a wall can be used to represent binary information. The two methods of representation are essentially different since different aspects of spatial symmetry are involved. A practical method of utilizing wall-rotation information coding can be effected by means of strips of thin magnetic film and nearby current conductors which are used to generate magnetic fields in specified directions at specified times and places. A shift register consists of a regular up-and-down domain pattern with M perpendicular to the long strip axis; no information is contained in the domain pattern itself, which only serves to separate spatially the information-bearing walls. Shifting is accomplished by two-phase clock pulses on a pair of shifting windings. Read-out requires the use of the operation of conditional erase, accomplished as follows: if two walls of the same sense are brought together they form a double wall which can subsequently be separated into two walls; if the walls are of the opposite sense they will destroy one another upon being brought together. Thus, erasure occurs on condition that two walls have opposite sense. View full abstract»

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  • Cryosar Memory Design

    Page(s): 712 - 717
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    The compensated cryosar is a negative-resistance two-terminal device utilizing a bulk effect in germanium at liquid helium temperatures. Its bistable nature, and the ease with which it can be fabricated in large arrays recommend it for application to computer memory systems. However, careful consideration of device and circuit parameters is necessary if a successful large memory is to be achieved. View full abstract»

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  • A Method for Resolving Multiple Responses in a Parallel Search File

    Page(s): 718 - 722
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    It is possible to build memories in which the contents of all registers are tested simultaneously, and in which there is a single indication of the presence or absence of any number of positive responses to the test criterion. A method is described for separately identifying the members of a set of responses by presenting sequences of tests which generate an identification number for each member. The testing algorithm is easily mechanized, and the number of tests required per item is approximately proportional to the logarithm of the number of file registers. The method also may be used to search for items with contents falling within arbitrary numerical ranges. View full abstract»

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  • Drum Organization for Strobe Addressing

    Page(s): 722 - 729
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    In strobe addressing, a pulse from the memory drum or disk forces the control unit to accept a program word. Strobe addressing for drums or disks costs less than 20 per cent of conventional addressing for real-time control programs, but becomes impractical for very complex problems. A comparison of various forms of strobe and conventional addressing shows that simple strobe addressing uses the memory as efficiently as conventional addressing if the problem can and must be solved in one revolution. By interlacing instructions with complete freedom for the program to switch interlaces, a strobe-addressed drum appears to have as many parallel bands as it has interlaces, thereby extending the advantages of strobe-addressing to more complex problems. Only minor changes in the program memory are necessary, and the arithmetic element and control unit remain essentially unchanged. The irregular interlace organization is described for an airborne computer with an 8-fold interlace, and its effectiveness is evaluated. In a test problem, this method reduces the size of the required memory by a factor of four and increases the effective computing speed fourfold. View full abstract»

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  • Computer Languages for Symbol Manipulation

    Page(s): 729 - 735
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    Complex, flexible, computer programs can be written easily in list-processing languages. Storage registers are linked together in arbitrary sequences to form lists and list structures, which are the units of the languages. Special provisions are made for recursive subroutines and for hierarchical programs. These particular languages have been used to write game-playing, problem-solving, and other ``intelligent'' Programs. View full abstract»

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  • Computer Synthesis of Character-Recognition Systems

    Page(s): 735 - 747
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    A SAP (Symbolic Assembly Program) package has been developed for the IBM 704 computer to simulate the logical tree of circuitry associated with a character-recognition device. The program has two major inputs: a particular set of logic statements (of AND and OR type) on cards, for flexibility, and tape reels of binary images of ideal or real characters. The output is the ``score'' of the logic: how many misjudgments it made on the images, what areas of the logic caused the misjudgments, and possible improvements of these areas. View full abstract»

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  • An Incremental Computer Technique for Solving Coordinate-Rotation Equations

    Page(s): 748 - 751
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    A method for solving coordinate rotation equations on an incremental digital computer is described in this paper. The method employs the basic incremental techniques used in a digital differential analyzer (DDA). However, the method differs from the usual DDA approach in that it takes full advantage of the possibilities for combining ``remainder,'' or ``R'' registers. This results in a reduction of digital storage-capacity requirements. Further, techniques are employed which, because of the specific nature of the application, permit additional reductions in storage requirements. View full abstract»

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  • Two-Level Correlation on an Analog Computer

    Page(s): 752 - 758
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    It has been known for some time that an approximate correlation analysis of a random process can be performed using quantized values of the signal. The simplest form possible is a two-level correlation, wherein merely the polarities of the process at two sampling times, T1 and T2=T1+¿ are compared. This report describes a study of this technique, using analog-computer circuitry; it is an interesting example of how existing electronic analog computers can implement essentially digital functions in making accurate statistical measurements. View full abstract»

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  • Soviet Cybernetics and Computer Sciencesߞ1960

    Page(s): 759 - 776
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    This is the author's report of his visit to the Soviet Union in June and July, 1960. The purpose of the trip was to attend the First Congress of the International Federation of Automatic Control (IFAC) as an official American delegate. The author also arranged to meet with certain scientists in psychology, physiology, and the computer sciences, and to visit some Russian research institutions doing work in these areas. Soviet research in cybernetics, neuro-cybernetics, artificial intelligence, mechanical translation, and automatic programming are discussed, and new developments in Soviet computing machines are described. The author describes his discussions with several important Soviet personalities in the computer sciences, which dealt with their particular work and the work of their research institutions. He concludes that Soviet research in the computer sciences lags behind Western developments, but that the gap is neither large nor based on a lack of understanding of fundamental principles. He believes that the Soviets will move ahead rapidly if and when priority, in terms of accessibility to computing machines, is given to their research. View full abstract»

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Aims & Scope

This Transactions ceased publication in 1962. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope