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IEEE Design & Test of Computers

Issue 4 • Date July-Aug. 2009

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • Front Covers 
  • Table of Contents

    Publication Year: 2009, Page(s): c2
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  • Toc 
  • Departments [Table of Contents]

    Publication Year: 2009, Page(s): 1
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  • From the EIC: Building and verifying hardware at a higher level of abstraction

    Publication Year: 2009, Page(s): 2
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  • Call for Papers

    Publication Year: 2009, Page(s): 3
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  • Society Information

    Publication Year: 2009, Page(s): 7
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  • Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design

    Publication Year: 2009, Page(s):4 - 6
    Cited by:  Papers (4)
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  • An Introduction to High-Level Synthesis

    Publication Year: 2009, Page(s):8 - 17
    Cited by:  Papers (57)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB) | HTML iconHTML

    High-level synthesis raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements. This article gives an overview of state-of-the-art HLS techniques and tools. View full abstract»

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  • High-Level Synthesis: Past, Present, and Future

    Publication Year: 2009, Page(s):18 - 25
    Cited by:  Papers (88)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6788 KB) | HTML iconHTML

    This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design. View full abstract»

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  • Virtual Roundtable: User Perspectives

    Publication Year: 2009, Page(s):26 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3140 KB) | HTML iconHTML

    Several high-level-synthesis users, whose experience spans the range of commercially available HLS tools, were recently invited to a virtual roundtable to share their HLS experiences. The various questions provide context for how they have used HLS, the benefits they have derived from it, and areas for improvement that they would like to see in the future. View full abstract»

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  • Lessons and Experiences with High-Level Synthesis

    Publication Year: 2009, Page(s):34 - 45
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (187 KB) | HTML iconHTML

    Electronic system level (ESL) design has attracted considerable attention in the past few years, and high level synthesis is a significant component of ESL design. Despite advances in HLS algorithms, the RTL remains the dominant specification and synthesis level. This article is a designer's perspective on the benefits and challenges of using commercially available HLS tools. They discuss their im... View full abstract»

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  • High-Level Dataflow Transformations Using Taylor Expansion Diagrams

    Publication Year: 2009, Page(s):46 - 57
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    This article provides an overview of a canonical representation for arithmetic expressions and how it can be used to obtain various factorizations of such expressions to optimize them. The applicability of the approach is demonstrated in a high-level synthesis flow. View full abstract»

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  • Hardware Coprocessor Synthesis from an ANSI C Specification

    Publication Year: 2009, Page(s):58 - 67
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1576 KB) | HTML iconHTML

    This article shows how design space exploration can be realized through high-level synthesis.It presents a case study of a hardware implementation of the advanced encryption standard (AES) Rijindael algorithm. Starting from algorithmic specification, it generate various architectures by using the C2R compiler. View full abstract»

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  • Subword Switching Activity Minimization to Optimize Dynamic Power Consumption

    Publication Year: 2009, Page(s):68 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (819 KB) | HTML iconHTML

    This article presents an original high-level synthesis approach that addresses the problem of dynamic power consumption in data-dominated applications. The proposed scheduling and binding algorithms deal with the switching-activity information, at the variable subword level, to reduce the number of commutations. View full abstract»

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  • Statistical High-Level Synthesis under Process Variability

    Publication Year: 2009, Page(s):78 - 87
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (610 KB) | HTML iconHTML

    CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys recent progress in the statistical high-level synthesis area. View full abstract»

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  • Functional Equivalence Verification Tools in High-Level Synthesis Flows

    Publication Year: 2009, Page(s):88 - 95
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (653 KB) | HTML iconHTML

    High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs. View full abstract»

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  • CEDA Currents

    Publication Year: 2009, Page(s):96 - 98
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  • Departments 
  • Design Automation Technical Committee Newsletter

    Publication Year: 2009, Page(s): 99
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  • Book Review: A physical-design picture book

    Publication Year: 2009, Page(s):100 - 101
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  • Departments 
  • Test Technology TC Newsletter

    Publication Year: 2009, Page(s):102 - 103
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  • The Last Byte: The HLS tipping point

    Publication Year: 2009, Page(s): 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB) | HTML iconHTML

    This column presents several reasons why the authors feel that the tipping point of high-level synthesis is getting close, including the needs of design space exploration, power optimization, behavior-level physical synthesis, and integrated design and validation. View full abstract»

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  • [Advertisement - Back cover]

    Publication Year: 2009, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2009, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty