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Micro, IEEE

Issue 4 • Date July-Aug. 2009

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Publication Year: 2009 , Page(s): c1
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  • [Front cover]

    Publication Year: 2009 , Page(s): c2
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  • Editor in Chief

    Publication Year: 2009 , Page(s): 1
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  • Micro Economics: Soccer Mom Messaging Is the Poetry of Our Age

    Publication Year: 2009 , Page(s): 2 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    It is too expensive to erase the digital past. In brief, the modern Internet lacks an undo button. View full abstract»

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  • Call for Papers

    Publication Year: 2009 , Page(s): 4
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  • Guest Editors' Introduction: Hot Interconnects

    Publication Year: 2009 , Page(s): 5 - 7
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  • Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

    Publication Year: 2009 , Page(s): 8 - 21
    Cited by:  Papers (34)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1527 KB) |  | HTML iconHTML  

    Silicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks. View full abstract»

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  • Practical High-Throughput Crossbar Scheduling

    Publication Year: 2009 , Page(s): 22 - 35
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2122 KB) |  | HTML iconHTML  

    A practical deterministic crossbar scheduler achieves almost full throughput without being heavily affected by short virtual output queues or traffic burstiness. Simple additions offer deterministic service guarantees and distribute the bandwidth of congested links in a weighted, fair manner. Input-queued crossbars are the common building blocks in Internet routers, data center and high-performance computing interconnects, and on-chip networks. These crossbars often contain no buffers, which saves valuable chip area. Arriving packets issue requests to a central scheduler. While waiting for the scheduler to grant their requests, packets wait at input packet buffers in front of the crossbar. To isolate traffic for different outputs, these input buffers are often organized as virtual output queues (VOQs). View full abstract»

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  • Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology

    Publication Year: 2009 , Page(s): 36 - 47
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2677 KB) |  | HTML iconHTML  

    To bring the benefits of CMT to larger workloads, these systems had to scale beyond a single socket. Because CMT requires massive memory bandwidth to achieve adequate throughput performance, the challenge was to develop a coherency link and fabric that would allow performance to scale along with thread count in a multinode (that is, multisocket) system. In this article CoHub's coherency scheme, ASIC design, and transtransaction flows, and discussion of the engineering challenges created by 800-MHz operation and a six-stage pipeline budget is presented. The basic principles embodied in the multinode coherency protocol and CoHub design will be important building blocks for future multinode CMT systems with higher node counts. View full abstract»

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  • Express Virtual Channels with Capacitively Driven Global Links

    Publication Year: 2009 , Page(s): 48 - 61
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (978 KB) |  | HTML iconHTML  

    Networks on chip must deliver high bandwidth at low latencies while keeping within a tight power envelope. Using express virtual channels for flow control improves energy-delay throughput by letting packets bypass intermediate routers, but EVCS have key limitations. Nochi (NoC with hybrid interconnect) overcomes these limitations by transporting data payloads and control information on separate planes, optimized for bandwidth and latency respectively. View full abstract»

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  • A High-Speed Optical Multidrop Bus for Computer Interconnections

    Publication Year: 2009 , Page(s): 62 - 73
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4105 KB) |  | HTML iconHTML  

    Signal integrity constraints of high-speed electronics have made multidrop electrical buses infeasible. This high-speed alternative uses hollow metal waveguides and pellicle beam splitters that interconnect modules attached to the bus. With 1 mw of laser power, the bus can interconnect eight modules at 10 gbps per channel and achieves an aggregate bandwidth of more than 25 gbytes per second with 10-bit-wide signaling paths. View full abstract»

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  • Photonic NoCs: System-Level Design Exploration

    Publication Year: 2009 , Page(s): 74 - 85
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2388 KB) |  | HTML iconHTML  

    Network-on-chip is a key enabling technology to address the challenges of interconnecting the increasing number of cores in emerging chip multiprocessors. By leveraging recent advances in the CMOS integration of photonic devices and the unique properties of the optical medium, photonic NoCs offer a promising solution to meet the communication requirements of chip multiprocessors with minimal draw from their power budget. View full abstract»

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  • Micro Law: An End to the Rambus Skullduggery Saga

    Publication Year: 2009 , Page(s): 86
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  • Micro Review: Twitter

    Publication Year: 2009 , Page(s): 87 - 88
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  • [Advertisement - Back cover]

    Publication Year: 2009 , Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2009 , Page(s): c4
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Aims & Scope

High-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center