# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 53
• ### [Front cover]

Publication Year: 2009, Page(s): C1
| PDF (190 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2009, Page(s): C2
| PDF (51 KB)

Publication Year: 2009, Page(s):1781 - 1783
| PDF (67 KB)
• ### Special Issue on Compact Interconnect Models for Gigascale Integration

Publication Year: 2009, Page(s):1784 - 1786
| PDF (106 KB) | HTML
• ### Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies

Publication Year: 2009, Page(s):1787 - 1798
Cited by:  Papers (20)
| | PDF (1321 KB) | HTML

The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) an... View full abstract»

• ### Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

Publication Year: 2009, Page(s):1799 - 1821
Cited by:  Papers (204)  |  Patents (2)
| | PDF (2018 KB) | HTML

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the stat... View full abstract»

• ### Compact Physics-Based Circuit Models for Graphene Nanoribbon Interconnects

Publication Year: 2009, Page(s):1822 - 1833
Cited by:  Papers (106)
| | PDF (2522 KB) | HTML

Physics-based equivalent circuit models are presented for armchair and zigzag graphene nanoribbons (GNRs), and their conductances have been benchmarked against those of carbon nanotubes and copper wires. Atomically thick GNRs with smooth edges can potentially have smaller resistances compared with copper wires with unity aspect ratios for widths below 8 nm and stacks of noninteracting GNRs can hav... View full abstract»

• ### Inductance in One-Dimensional Nanostructures

Publication Year: 2009, Page(s):1834 - 1839
Cited by:  Papers (9)
| | PDF (184 KB) | HTML

The physical origin of kinetic inductance is examined for 1-D nanostructures, where the Fermi liquid theory prevails. In order to have appreciable kinetic inductance, ballistic transport must exist, with no inelastic scattering inside the nanowires. Kinetic inductance is assigned to the nanowire itself and independent of its surroundings, whereas magnetic inductance is assigned to the nanowire and... View full abstract»

• ### Interconnect Modeling: A Physical Design Perspective

Publication Year: 2009, Page(s):1840 - 1851
Cited by:  Papers (4)
| | PDF (780 KB) | HTML

Variability, reliability, and design size are becoming major difficulties in system-on-a-chip (SoC) designs as the scaling of semiconductor technology advances. Techniques for interconnect modeling and analysis in designing advanced SoCs are discussed from the design-automation point of view. Importance of interconnect modeling in modern chip-design flows is first summarized. State-of-the-art phys... View full abstract»

• ### Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond

Publication Year: 2009, Page(s):1852 - 1861
Cited by:  Papers (12)
| | PDF (991 KB) | HTML

Challenges and issues with the scaling of low-k/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance-capacitance (GSRC) model is proposed to compare the interconnect performance at ... View full abstract»

• ### Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Publication Year: 2009, Page(s):1862 - 1872
Cited by:  Papers (23)
| | PDF (1327 KB) | HTML

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal-oxide-semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these g... View full abstract»

• ### Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Publication Year: 2009, Page(s):1873 - 1881
Cited by:  Papers (113)
| | PDF (951 KB) | HTML

Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expres... View full abstract»

• ### The Impact of On-Chip Interconnections on CMOS RF Integrated Circuits

Publication Year: 2009, Page(s):1882 - 1890
Cited by:  Papers (11)
| | PDF (1144 KB) | HTML

Achieving power- and area-efficient fully integrated transceivers is one of the major challenges faced when designing high-frequency electronic circuits suitable for biomedical applications or wireless sensor networks. The power losses associated with the parasitics of on-chip inductors, transistors, and interconnections have posed design challenges in the full integration of power-efficient CMOS ... View full abstract»

• ### A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology

Publication Year: 2009, Page(s):1891 - 1896
Cited by:  Papers (3)
| | PDF (442 KB) | HTML

In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thic... View full abstract»

• ### InP DHBT Process in Transferred-Substrate Technology With $f_{t}$ and $f_{max}$ Over 400 GHz

Publication Year: 2009, Page(s):1897 - 1903
Cited by:  Papers (18)
| | PDF (1091 KB) | HTML

In this paper, a double heterojunction bipolar transistor (DHBT) process has been developed in transferred-substrate (TS) technology to optimize high-frequency performance. It provides an aligned lithographic access to frontside and backside of the device to eliminate dominant transistor parasitics. The transistors of 0.8 times 5-mum2 emitter mesa feature ft = 410 GHz and f View full abstract»

• ### Gate-Recess Technology for InAs/AlSb HEMTs

Publication Year: 2009, Page(s):1904 - 1911
Cited by:  Papers (17)
| | PDF (1158 KB) | HTML

The gate-recess technology for Si delta-doped InAs/AlSb high-electron-mobility transistors (HEMTs) has been investigated by combining atomic force microscopy (AFM) inspection of the gate-recess versus time with electrical device characterization. Deposition of the gate metal on the In0.5Al0.5As protection layer or on the underlying AlSb Schottky layer resulted in devices suff... View full abstract»

• ### Electrooptical Analysis of Effects Induced by Floating Metallic Interlayers in Organic LEDs

Publication Year: 2009, Page(s):1912 - 1918
Cited by:  Papers (3)
| | PDF (1370 KB) | HTML

The aim of this paper is to investigate the electrical and optical property modifications that can be related to the presence of a nanometric metallic layer at the interface between two organic emissive materials in a stacked structure. For purposes of comparison, reference devices have also been analyzed to emphasize the increase of electrical switching and hysteresis behaviors in current-voltage... View full abstract»

• ### Quantitative Analysis of Dopant Distribution and Activation Across p-n Junctions in AlGaAs/GaAs Light-Emitting Diodes Using Off-Axis Electron Holography

Publication Year: 2009, Page(s):1919 - 1923
Cited by:  Papers (4)
| | PDF (587 KB) | HTML

Off-axis electron holography has been used to measure the electrostatic potential profile across the p-n junction of an AlGaAs/GaAs light-emitting diode with linearly graded triangular AlGaAs barriers. Simulations of the junction profile showed small discrepancies with experiment when the nominal dopant concentrations of Si and Be impurities were used. Revised simulations reproduced the measuremen... View full abstract»

• ### Microcrystalline-Silicon Transistors and CMOS Inverters Fabricated Near the Transition to Amorphous-Growth Regime

Publication Year: 2009, Page(s):1924 - 1929
Cited by:  Papers (9)
| | PDF (623 KB) | HTML

Thin-film transistors (TFTs) are core elements of novel display media for large-area electronic applications. Microcrystalline-silicon TFTs prepared at low temperatures (150degC - 200degC) have recently gained much attention as potential elements for such applications due to their high charge carrier mobilities exceeding 10 cm2/V middots. Understanding the relationship between structura... View full abstract»

• ### AC Microplasma Device With a Cylindrical Hollow Electrode for Improving Luminous Efficacy

Publication Year: 2009, Page(s):1930 - 1934
Cited by:  Papers (1)
| | PDF (578 KB) | HTML

In this paper, a device utilizing the hollow cathode discharge is demonstrated to diagnose the possibility of improving luminous efficacy of a microplasma device. A series of experiments is conducted by measuring luminous efficacy, which is an important factor in display devices, in accordance with specifications of the cylindrical hollow and gas pressure. The proposed structure has two electrodes... View full abstract»

• ### CMOS-SOI-MEMS Transistor for Uncooled IR Imaging

Publication Year: 2009, Page(s):1935 - 1942
Cited by:  Papers (21)  |  Patents (4)
| | PDF (621 KB) | HTML

This paper reports the design, fabrication technology, post-CMOS micromachining and characterization of CMOS-silicon-on-insulator (SOI)-microelectromechanical system (MEMS) transistors. The thermally isolated micromachined CMOS-SOI-MEMS transistor reported here is designed for uncooled infrared (IR) sensing and is dubbed here as ldquoTMOS.rdquo The measured dc and noise electrical characteristics ... View full abstract»

• ### A New NBTI Model Based on Hole Trapping and Structural Relaxation in MOS Dielectrics

Publication Year: 2009, Page(s):1943 - 1952
Cited by:  Papers (25)
| | PDF (1043 KB) | HTML

Negative bias temperature instability (NBTI) is one of the major reliability concerns for analog and digital MOS devices. NBTI understanding and modeling is receiving a growing interest for failure prediction, depending on the temperature and duty cycle of dynamic-stress conditions. In this framework, we present a new NBTI model based on hole trapping and thermally activated relaxation. The model ... View full abstract»

• ### P-Channel MOSFETs on 4H-SiC {0001} and Nonbasal Faces Fabricated by Oxide Deposition and $hbox{N}_{2}hbox{O}$ Annealing

Publication Year: 2009, Page(s):1953 - 1958
Cited by:  Papers (17)
| | PDF (222 KB) | HTML

In this paper, we have investigated 4H-SiC p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited SiO2 followed by N2O annealing. In addition to deposited oxides, dry-O2-grown oxides and N2O-grown oxides were also adopted as the gate oxides of SiC p-channel MOSFETs. The MOSFETs have been fabricated on the 4H-SiC (0001), (00... View full abstract»

• ### On the Scaling of Flash Cell Spacer for Gate Disturb and Charge Retention Optimization

Publication Year: 2009, Page(s):1959 - 1965
Cited by:  Papers (4)  |  Patents (2)
| | PDF (630 KB) | HTML

Self-aligned contact processes enable aggressive scaling of the cell sidewall spacer for advanced nor Flash technology. Spacer scaling can increase bake-induced charge loss/gain and gate disturb. High-quality spacer dielectrics are necessary to reduce the bake shift and gate disturb effects. The peak field at the floating gate corner, in particular, plays a significant role in gate disturb. View full abstract»

• ### Second-Bit-Effect-Free Multibit-Cell Flash Memory Using $hbox{Si}_{3} hbox{N}_{4}/hbox{ZrO}_{2}$ Split Charge Trapping Layer

Publication Year: 2009, Page(s):1966 - 1973
Cited by:  Papers (2)
| | PDF (889 KB) | HTML

In this paper, a Si3N4/ZrO2 split charge trapping layer (SCTL) is proposed for multibit-cell Flash memory. The complementary potential wells of Si3N4/ZrO2 storage nodes enable independent node control when the Fowler-Nordheim (F-N) method is applied for programming/erasing (P/E). Experiment and simulation results suggest that the 2-... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy