By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sept. 2009

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (48 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2009 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (43 KB)  
    Freely Available from IEEE
  • Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy

    Publication Year: 2009 , Page(s): 1281 - 1294
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1324 KB) |  | HTML iconHTML  

    This paper presents MOJITO-R, a tool that performs variation-aware structural synthesis of analog circuits. It returns trustworthy topologies by searching across a space of thousands of possible topologies defined by hierarchically organized analog structural building blocks. ldquoStructural homotopyrdquo conducts search at several objective-function tightening levels (numbers of process corners) ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips

    Publication Year: 2009 , Page(s): 1295 - 1306
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (529 KB) |  | HTML iconHTML  

    Due to recent advances in microfluidics technology, digital microfluidic biochips and their associated computer-aided-design problems have gained much attention, most of which has been devoted to direct-addressing biochips. In this paper, we solve the droplet routing problem under the more scalable cross-referencing biochip paradigm. We propose the first droplet routing algorithm that directly sol... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

    Publication Year: 2009 , Page(s): 1307 - 1320
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1596 KB) |  | HTML iconHTML  

    Metallic carbon nanotubes (CNTs) pose a major barrier to the design of digital logic circuits using CNT field-effect transistors (CNFETs). Metallic CNTs create source to drain shorts in CNFETs, resulting in undesirable effects such as excessive leakage and degraded noise margins. No known CNT growth technique guarantees 0% metallic CNTs. Therefore, special processing techniques are required for re... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of Data-Flow Computations Using Canonical TED Representation

    Publication Year: 2009 , Page(s): 1321 - 1333
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    An efficient graph-based method to optimize polynomial expressions in data-flow computations is presented. The method is based on the factorization, common-subexpression elimination, and decomposition of algebraic expressions performed on a canonical Taylor expansion diagram representation. It targets the minimization of the latency and hardware cost of arithmetic operators in the scheduled implem... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling

    Publication Year: 2009 , Page(s): 1334 - 1347
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1409 KB) |  | HTML iconHTML  

    Dynamic voltage scaling (DVS) is a popular energy-saving technique for real-time tasks. The effectiveness of DVS critically depends on the accuracy of workload estimation, since DVS exploits the slack or the difference between the deadline and execution time. Many existing DVS techniques are profile based and simply utilize the worst-case or average execution time without estimation. Several recen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Power Network Analysis Considering Multidomain Clock Gating

    Publication Year: 2009 , Page(s): 1348 - 1358
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (689 KB) |  | HTML iconHTML  

    In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily conve... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A -Stable and L -Stable High-Order Integration Methods for Solving Stiff Differential Equations

    Publication Year: 2009 , Page(s): 1359 - 1372
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1047 KB) |  | HTML iconHTML  

    This paper describes a new A- and L-stable integration method for simulating the time-domain transient response of nonlinear circuits. The proposed method, which is based on the Obreshkov formula, can be made of arbitrary high order while maintaining the A-stability property. The new method allows for the adoption of higher order integration methods for the transient analysis of electronic ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs

    Publication Year: 2009 , Page(s): 1373 - 1386
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (717 KB) |  | HTML iconHTML  

    In this paper, we present a performance and thermal-aware Steiner routing algorithm for three-dimensional (3-D) stacked integrated circuits. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that our 3-D tree construction involves minimization of two-variable Elmore... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Real-Time Lossless Compression for Silicon Debug

    Publication Year: 2009 , Page(s): 1387 - 1400
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (986 KB) |  | HTML iconHTML  

    Silicon debug is becoming a key step in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the lack of observability for the internal circuit nodes during silicon debug, embedded logic analysis enables real-time data acquisition from a limited number of internal signals. In this paper, we propose a novel architectu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults

    Publication Year: 2009 , Page(s): 1401 - 1413
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1333 KB) |  | HTML iconHTML  

    In this paper, we propose a new test-generation method for delay faults considering crosstalk-induced delay effects, based on a conventional delay automatic-test-pattern-generation (ATPG) technique in order to reduce the complexity of previous ATPG algorithms and to consider multiple-aggressor crosstalk faults to maximize the noise of the victim line. Since the proposed ATPG for crosstalk-induced ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal Test Margin Computation for At-Speed Structural Test

    Publication Year: 2009 , Page(s): 1414 - 1423
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (563 KB) |  | HTML iconHTML  

    In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called test margin . There are many good reasons for margin, including voltage and temperature requi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets

    Publication Year: 2009 , Page(s): 1424 - 1428
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    We extend the concept of forward-looking reverse order fault simulation to n-detection test sets. Forward-looking reverse order fault simulation is an efficient static test compaction process similar to reverse order fault simulation, but with the advantage that it results in test sets that do not contain any unnecessary tests. The application of test compaction procedures to n-detec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling

    Publication Year: 2009 , Page(s): 1428 - 1432
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    Accurate statistical modeling and simulation are keys to ensure that integrated circuits (ICs) meet the specifications over the stochastic variations that are inherent in IC manufacturing technologies. Backward propagation of variance (BPV) is a general technique for statistical modeling of semiconductor devices. However, the BPV approach assumes that statistical fluctuations are not large so that... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2009 , Page(s): 1433
    Save to Project icon | Request Permissions | PDF file iconPDF (25 KB)  
    Freely Available from IEEE
  • Why we joined ... [advertisement]

    Publication Year: 2009 , Page(s): 1434
    Save to Project icon | Request Permissions | PDF file iconPDF (205 KB)  
    Freely Available from IEEE
  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2009 , Page(s): 1435
    Save to Project icon | Request Permissions | PDF file iconPDF (345 KB)  
    Freely Available from IEEE
  • Leading the field since 1884 [advertisement]

    Publication Year: 2009 , Page(s): 1436
    Save to Project icon | Request Permissions | PDF file iconPDF (223 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2009 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (27 KB)  
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu