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Computers & Digital Techniques, IET

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Computers & Digital Techniques, IET

Issue 5 • Date September 2009

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Title History

Networks on chips [editorial]

Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis

Bandwidth-aware routing algorithms for networks-on-chip platforms

Low-distance path-based multicast routing algorithm for network-on-chips

Joint multicast routing and network design optimisation for networks-on-chip

Efficient implementation of distributed routing algorithms for NoCs

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

Impact of on-chip network parameters on nuca cache performances

Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor

Processing while routing: a network-on-chipbased parallel system

Application modelling and hardware description for network-on-chip benchmarking

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