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Design & Test of Computers, IEEE

Issue 1 • Date March 1993

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Displaying Results 1 - 9 of 9
  • Using march tests to test SRAMs

    Publication Year: 1993 , Page(s): 8 - 14
    Cited by:  Papers (118)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (723 KB)  

    A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models. The likelihood that the different types of faults will occur is demonstrated using inductive fault analysis and physical defect analysis. A set of march tests is discussed, together with methods to make composite tests for collections of fault tapes. Empirical results showing the f... View full abstract»

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  • A new testing acceleration chip for low-cost memory tests

    Publication Year: 1993 , Page(s): 15 - 19
    Cited by:  Papers (13)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (373 KB)  

    It is argued that the development of semiconductor memories has reached a turning point. In the multimegabit dynamic random access memories (DRAMs) of the future, major factors contributing to the chip cost are process complexity, die size, equipment cost, and test cost. If conventional test methods are used, test costs will grow at an especially rapid rate. A memory test concept called the testin... View full abstract»

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  • Generating tests for delay faults in nonscan circuits

    Publication Year: 1993 , Page(s): 20 - 28
    Cited by:  Papers (22)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (838 KB)  

    A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault perfor... View full abstract»

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  • Estimating the complexity of synthesized designs from FSM specifications

    Publication Year: 1993 , Page(s): 30 - 35
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (739 KB)  

    A procedure for estimating the complexity of synthesized designs from finite-state machine (FSM) specifications is described. Incorporating this estimate in the data path synthesis stage allows a trade-off between data path and control logic, resulting in high quality designs in terms of synthesized logic area. It is shown that the estimation process takes 650 to 3000 times less CPU time than the ... View full abstract»

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  • An automatic netlist-to-schematic generator

    Publication Year: 1993 , Page(s): 36 - 41
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (494 KB)  

    The N2S schematic generator, which uses a variable-ordering technique in the initial placement phase and simple heuristics in the final placement phase, is described. Its channel-routing techniques result in signal routing with minimal crossovers. The authors demonstrate the efficiency of N2S by applying it to a set of benchmark sequential circuits.<> View full abstract»

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  • Test sets and reject rates: all fault coverages are not created equal

    Publication Year: 1993 , Page(s): 42 - 51
    Cited by:  Papers (34)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (926 KB)  

    The use of stuck-at-fault coverage for estimating overall quality levels is examined. Data from a part tested with both functional and scan tests are analyzed and compared with quality predictions generated by three existing theoretical models. It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significant... View full abstract»

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  • Fault isolation in an integrated diagnostic environment

    Publication Year: 1993 , Page(s): 52 - 66
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1234 KB)  

    The use of information flow models to conduct efficient fault isolation strategies is described. Of particular concern is optimizing diagnosis to minimize some objective cost function. A technique that can include multiple cost criteria such as test time, skill level, and failure frequency, as well as information value, is discussed.<> View full abstract»

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  • Applications of a laser-induced plasma pathway to testing of electronic modules

    Publication Year: 1993 , Page(s): 67 - 72
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (641 KB)  

    The authors discuss further developments and experimental applications of an in situ noncontact testing (NCT) system for printed-wire boards (PWBs). The results demonstrate the system's ability to overdrive logic circuits using the signal injection, making it an excellent means for analyzing operating hardware without disruption. The results also indicate that the NCT probe can serve well as a low... View full abstract»

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  • A tutorial on built-in self-test. I. Principles

    Publication Year: 1993 , Page(s): 73 - 82
    Cited by:  Papers (99)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (868 KB)  

    An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty