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Consumer Electronics, IEEE Transactions on

Issue 1 • Date Feb 1993

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Displaying Results 1 - 9 of 9
  • Design of iterative learning controller with VCR servo system

    Page(s): 13 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    An iterative learning control law with feedback is proposed, and the convergence of the algorithm is proved using the 2-D system stability theory. Its effectiveness is illustrated by an experiment on a video cassette recorder (VCR) servo system. The experimental results show considerable reduction of periodic noise and of its multiple frequency components. Offset error is also reduced. The method is expected to be applicable for other automation systems with periodic disturbances and/or periodic inputs for which exact tracking is desirable and uncertainty in modeling is inevitable View full abstract»

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  • A study on high efficiency coding of HDTV at 50 Mbps

    Page(s): 49 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    High-efficiency techniques for encoding HDTV signals at 50 Mb/s are proposed. An adaptive chrominance interpolation method and an adaptive chrominance decimation method are discussed. It is shown that the distortion of decimation can be decreased and visible distortion can be reduced. Some pictures using these schemes were encoded by computer simulation, and it was confirmed that the processed pictures are adequate for consumer use View full abstract»

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  • MOS circuits for median filtering applications

    Page(s): 25 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    Several circuit configurations to sort or detect the highest voltage in a range of input signals are presented. These MOS-based circuits can generally be used as median filters in image processing to sort out the median pixel in a neighborhood of pixels. They can be generalized to n-input sorter circuits for generating the median at the output. They can also be used in maximum-voltage detection applications and in neural network systems where the winner-take-all subcircuit is required View full abstract»

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  • A single-chip controller for digital answering machines

    Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A single-chip controller for digital answering machines is introduced. Only two other devices, an audio quality DRAM (ARAM) and a codec, are needed to implement all the digital parts of such an answering machine. The device performs voice compression and decompression algorithms, dual-tone multifrequency (DTMF) detection, voice synthesis, and control functions of digital answering machines View full abstract»

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  • Optical fibre transmission of video and audio signals using square wave frequency modulation

    Page(s): 33 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    The authors report the design, construction and performance of a square wave frequency modulation (SWFM) technique for point-to-point transmission of video and voice channels over 1 km of fiber. The results indicate that the SWFM system is a bandwidth-efficient and low-cost alternative to more complex and expensive digital systems requiring far greater bandwidth View full abstract»

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  • CD-ROM player for business presentations

    Page(s): 57 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    A portable CD-ROM player with compressed color graphics and sound was developed. The CD-ROM player, which provides a synchronized presentation function and a hyperlinked database function, is a personal multimedia tool for business presentations and educational publications View full abstract»

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  • Multiprocessor DSP architectures that implement the FCT based JPEG still picture image compression algorithm with arithmetic coding

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    Several parallel pipelined digital signal processor (DSP) architectures that implement the fast cosine transform (FCT)-based Joint Photographers Expert Group (JPEG) still picture image compression algorithm with arithmetic coding for entropy coding are described. The extended JPEG image compression algorithm's average execution time, when compressing and decompressing a 256×256 pixel monochrome still image, varied from 0.61 s to 0.12 s in architectures that contained from one to six processors. A common bus DSP multiprocessor system capable of meeting the critical timing requirements of digital image compression/decompression applications is also presented. In an effort to maximize DSP utilization, a simple static load distribution method is provided for assigning the load to the individual DSPs. These parallel pipelined DSP architectures can be used for a wide range of applications, including the MPEG implementation for video coding View full abstract»

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  • Implementation of an adaptive transform decoder for high-quality audio on a 16-bit DSP chip

    Page(s): 40 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    A real-time stereo digital audio decoder based on one 16-b digital signal processor (DSP) chip, implementing the decoder portion of an audio compression system, is described. The roundoff-sensitive portions of the decoder include pre multiplier and conventional inverse FFT operations, which have been efficiently coded with mixed-precision 16-b by 32-b multiplies with 32-b accumulations. Compared with a 16-b single-precision implementation, a moderate increase in DSP CPU utilization is incurred. Results indicate that the dynamic range of the 16-b DSP decoder is currently within 1 to 3 dB of the limitations imposed by high-quality 16-b A/D and D/A converters View full abstract»

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  • Smart card reader

    Page(s): 6 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    A PC-based smart card reader designed and fabricated for cards that conform to the ISO 7816 standard is described. The reader, which is linked to the PC standard parallel port, consists of three modules: the hardware that serves as the physical interface between the smart card and the PC, the software driver interface between the card and the PC, and the application program. It makes use of the hardware resources of the PC together with a software-based driver to control the communication protocol between the smart card and the reader View full abstract»

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Aims & Scope

The primary purpose for publishing the Transactions of the Consumer Electronics Society is to present to the membership and the engineering community in general, papers on new technology oriented to Consumer Electronics.

 

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Meet Our Editors

Editor-in-Chief
R. Simon Sherratt
School Director for Teaching and Learning, School of Systems Engineering
The University of Reading
Reading, Berkshire  RG6 6AY  RG6 6AY  U.K.
r.s.sherratt@reading.ac.uk; sherratt@ieee.org
Phone:+44 (0) 118 3788588
Fax:+44 (0) 118 3788583