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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug. 2009

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Displaying Results 1 - 25 of 33
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2009 , Page(s): C2
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    Freely Available from IEEE
  • Circuit Modeling of High-Frequency Electrical Conduction in Carbon Nanofibers

    Publication Year: 2009 , Page(s): 1557 - 1561
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (295 KB) |  | HTML iconHTML  

    We show that the simplest possible circuit model of high-frequency electrical conduction in carbon nanofibers from 0.1 to 50 GHz is a frequency-independent resistor in parallel with a frequency-independent capacitor. The resistance is experimentally determined and represents the total dc resistance of the nanofiber and its contacts with the electrodes. The capacitance is obtained as a free parameter and has not been previously observed. The experimental method utilizes a ground-signal-ground test structure whose two-port scattering parameters (S-parameters) can be described to within plusmn0.5 dB and plusmn2deg using a simple lumped-element circuit model. The nanostructure is placed in the signal path of the test structure, and its equivalent circuit is deduced by determining what additional elements must be added to the test structure circuit model to reproduce the resulting changes in the S-parameters. This methodology is applicable to nanowires and nanotubes. View full abstract»

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  • Impact of Energy Quantization on the Performance of Current-Biased SET Circuits

    Publication Year: 2009 , Page(s): 1562 - 1566
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    The current-biased single electron transistor (SET) (CBS) is an integral part of almost all hybrid CMOS SET circuits. In this paper, for the first time, the effects of energy quantization on the performance of CBS-based circuits are studied through analytical modeling and Monte Carlo simulations. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics, although it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: negative differential resistance (NDR) and neuron cell, which use the CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. View full abstract»

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  • Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

    Publication Year: 2009 , Page(s): 1567 - 1578
    Cited by:  Papers (57)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1742 KB) |  | HTML iconHTML  

    Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects. View full abstract»

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  • Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

    Publication Year: 2009 , Page(s): 1579 - 1587
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1318 KB) |  | HTML iconHTML  

    A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter (phi) vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-phi vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation. View full abstract»

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  • Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

    Publication Year: 2009 , Page(s): 1588 - 1597
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1328 KB) |  | HTML iconHTML  

    The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits. View full abstract»

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  • A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

    Publication Year: 2009 , Page(s): 1598 - 1607
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1571 KB) |  | HTML iconHTML  

    A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance C of dominates around 25% of the intrinsic gate capacitance (C gint) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C of/C gint above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design. View full abstract»

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  • Gate-Induced Drain Leakage (GIDL) Improvement for Millisecond Flash Anneal (MFLA) in DRAM Application

    Publication Year: 2009 , Page(s): 1608 - 1617
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1778 KB) |  | HTML iconHTML  

    In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application. The periphery NMOS off current was reduced by 36%. This off-current improvement reduced the standby current by 5% in a DRAM functional test. The GIDL reductions for an NMOS array and periphery N- and PMOSs were 14.5%, 15%, and 39%, respectively. A model for GIDL improvement by MFLA application to DRAM production was proposed. It is believed that the main GIDL-impacted factor was the high electric field caused by defect-assisted tunneling and junction profile abruptness under the gate edge. Bright field and weak-beam dark-field TEM images showed perfect dislocation loops and fault dislocation loops staying in the {113} plane with a size of around 17 x 20 nm in the junction area. These defects could be one of the leakage sources for a defect-assisted trap charge, leading to trap-assisted tunneling. View full abstract»

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  • New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

    Publication Year: 2009 , Page(s): 1618 - 1623
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (999 KB) |  | HTML iconHTML  

    Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations. View full abstract»

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  • The \hbox {1}/f Noise and Random Telegraph Noise Characteristics in Floating-Gate nand Flash Memories

    Publication Year: 2009 , Page(s): 1624 - 1630
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1216 KB) |  | HTML iconHTML  

    We have characterized low-frequency noise (LFN) such as 1/f noise and random telegraph noise (RTN) in a NAND flash memory cell string for the first time and shown its fundamental properties. The NAND flash memory cells showed specific LFN characteristics under various conditions such as bit-line bias, word-line bias of a selected cell, and pass bias of the unselected cells in the NAND string. Also, LFN was investigated with the program/erase (P/E) cycling of a cell or all cells in a string, and maximum threshold voltage fluctuation of several tens of millivolts after ~100 000 cycles at the 70-nm technology node was shown. Finally, we predicted the effects of LFN in sub-70-nm NAND flash memories. View full abstract»

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  • Structural and Electrical Properties of Mn-Doped  \hbox {Bi}_{4}\hbox {Ti}_{3}\hbox {O}_{12} Thin Film Grown on  \hbox {TiN}/\hbox {SiO}_{2}/\hbox {Si} Substrate for RF MIM Capacitors

    Publication Year: 2009 , Page(s): 1631 - 1636
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (710 KB) |  | HTML iconHTML  

    Mn-doped Bi4Ti3O12 (M-B4T3) films were well formed on a TiN/SiO2/Si substrate at 200degC without buckling using RF magnetron sputtering. The leakage current density of these films was considerably influenced by the oxygen partial pressure (OPP), which was attributed to the presence of oxygen vacancies or oxygen interstitial ions. The film grown under 2.8-mtorr OPP showed the lowest leakage current density. The M-B4T3 films grown at 200degC showed a high dielectric constant of 38 with a low loss in both kilohertz and gigahertz ranges. The 39-nm-thick film showed a high capacitance density of 8.47 fF/mum2 at 100 kHz, and its temperature and quadratic voltage coefficients of capacitance were low at approximately 370 ppm/degC and 667 ppm/V2, respectively, with a low leakage current density of 7.8 times 10-8 A/cm2 at 2 V. Therefore, the M-B4T3 thin film grown on a TiN/SiO2/Si substrate is a good candidate material for high performance, radio frequency metal-insulator-metal capacitors. View full abstract»

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  • Low-Temperature Fabricated TFTs on Polysilicon Stripes

    Publication Year: 2009 , Page(s): 1637 - 1644
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1188 KB) |  | HTML iconHTML  

    This paper presents a novel approach to make high-performance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material. The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm2/Vmiddots (NMOS) and 128 cm2/Vmiddots (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized. The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration. View full abstract»

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  • Analysis of Selective Phosphorous Laser Doping in High-Efficiency Solar Cells

    Publication Year: 2009 , Page(s): 1645 - 1650
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    This paper focuses on the analysis of local phosphorous laser doping in high-efficiency solar cells. Those so-called selective emitters are intended to reduce the contact recombination and resistance in order to increase the solar conversion efficiency. Sample solar cells are prepared using laser chemical processing as the laser doping technique and analyzed via analytical models and suns-V oc measurements at high illumination densities. It can be shown that fully ohmic contacts can be manufactured on the investigated selective emitters which exhibit low dark saturation currents. The specific recombination current density of the local laser doping is determined experimentally to be < 8.5 times 10-13 A/cm2 for planar surfaces. View full abstract»

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  • Electron Mobility and Short-Channel Device Characteristics of SOI FinFETs With Uniaxially Strained (110) Channels

    Publication Year: 2009 , Page(s): 1651 - 1658
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (451 KB) |  | HTML iconHTML  

    We have successfully fabricated uniaxially strained SOI (SSOI) FinFETs with high electron mobility and low parasitic resistance. The high electron mobility enhancement on the (110) fin sidewall surfaces was obtained by utilizing effective subband engineering through uniaxial tensile strain along lang110rang, while the substantial reduction of the parasitic resistance was achieved by selective Si epitaxy on the source and drain regions. It was experimentally found that the electron mobility on the (110) sidewall surfaces was significantly enhanced (2.6times) and even surpassed the (100) universal mobility (1.2times). This high mobility enhancement is mainly attributed to the electron repopulation from fourfold valleys having a heavier mass along lang110rang to twofold valleys having a lighter one. In addition, the effective mass reduction of the twofold valleys due to conduction band warping and/or the suppressed surface roughness scattering can also be responsible for the mobility enhancement. Thanks to these high electron mobility enhancement and low parasitic resistance large performance enhancement of 35% was realized in uniaxially SSOI FinFETs with a gate length of 50 nm. This enhancement was evaluated to be as high as ~80% (= 35%/45%) of the intrinsic strain-induced enhancement of the short-channel device performance (45%) at the same strain level (0.8%, ~1.5 GPa) and gate length. View full abstract»

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  • Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

    Publication Year: 2009 , Page(s): 1659 - 1666
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1005 KB) |  | HTML iconHTML  

    A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias V bg, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). V bg only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 V/mum of the conventional SOI to 457 V/mum at V bg = 0 V, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO. View full abstract»

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  • Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs

    Publication Year: 2009 , Page(s): 1667 - 1673
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (754 KB) |  | HTML iconHTML  

    On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting. View full abstract»

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  • A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters

    Publication Year: 2009 , Page(s): 1674 - 1680
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    A simple semiempirical model ID(VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called ldquotop-of-the-barrier-transportrdquo model, and we refer to it as the ldquovirtual sourcerdquo (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage VGS = Vdd); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically Ioff at VGS = 0 V) and at high VDS; 5) total resistance at VDS = 0 V and VGS = Vdd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection. View full abstract»

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  • Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD- \hbox {Al}_{2}\hbox {O}_{3} Gate Dielectric

    Publication Year: 2009 , Page(s): 1681 - 1689
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1355 KB) |  | HTML iconHTML  

    In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p+-n and n+-p junctions exceeded three and four orders of magnitude (in the voltage range of plusmn1 V), respectively, with accompanying reverse leakages of ca. 10-2 and 10-4 A ldr cm-2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300degC boosted the device on-current, decreased the Al2O3/Ge interface states to 8 times 1011 cm-2 ldr eV-1, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm2 ldr V-1 ldr s-1 and > 103, respectively, for the p-FET (W/L = 100 mum/4 mum), while these values were less than 100 cm2 ldr V-1 ldr s-1 and ca. 103, respectively, for the n-FET (W/L = 100 mum/9 mum). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration. View full abstract»

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  • Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

    Publication Year: 2009 , Page(s): 1690 - 1697
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1858 KB) |  | HTML iconHTML  

    In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented. View full abstract»

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  • Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

    Publication Year: 2009 , Page(s): 1698 - 1704
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB) |  | HTML iconHTML  

    This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides (ges 4 nm) , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of SiO2 and Al2O3. By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells. View full abstract»

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  • High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields

    Publication Year: 2009 , Page(s): 1705 - 1711
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (661 KB) |  | HTML iconHTML  

    A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slot-type floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines. View full abstract»

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  • Modeling of Set/Reset Operations in NiO-Based Resistive-Switching Memory Devices

    Publication Year: 2009 , Page(s): 1712 - 1720
    Cited by:  Papers (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (781 KB) |  | HTML iconHTML  

    Resistive-switching memory (RRAM) devices are attracting a considerable interest in view of their back-end integration, fast programming, and high scalability. Prediction of the programming voltages and currents as a function of the operating conditions is an essential task for developing compact and numerical models able to handle a large number (106 - 109) of cells within an array. Based on recent experimental findings on the set and reset processes, we have developed physics-based analytical models for the set and reset operations in NiO-based RRAMs. Simulation results obtained by the analytical models were compared with experimental data for variable pulse conditions and were found consistent with data. The set transition is described by a threshold switching process at the broken conductive filament (CF), while the reset transition is viewed as a thermally driven dissolution and/or oxidation of the CF. Set and reset models are finally used for reliability predictions of failure times under constant-voltage stress (read disturb) and elevated-temperature bake (data retention). View full abstract»

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  • Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning

    Publication Year: 2009 , Page(s): 1721 - 1728
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1116 KB) |  | HTML iconHTML  

    Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered. View full abstract»

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  • Statistical Metrology of Metal Nanocrystal Memories With 3-D Finite-Element Analysis

    Publication Year: 2009 , Page(s): 1729 - 1735
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (842 KB) |  | HTML iconHTML  

    We study the parametrical yield of memory windows for the metal nanocrystal (NC) Flash memories with consideration of the 3-D electrostatics and channel percolation effects. Monte Carlo parametrical variation that accounts for the number and size fluctuations in NCs as well as channel length is used to determine the threshold voltage distribution and bit error rate for gate length scaling to 20 nm. Devices with nanowire-based channels are compared with planar devices having the same gate stack structure. Scalability prediction by 1-D analysis is found to be very different from 3-D modeling due to underestimation of effective NC coverage and failure to consider the 3-D nature of the channel percolation effect. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego