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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 8 • Date Aug. 2009

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Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2009 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (43 KB)  
    Freely Available from IEEE
  • Dependent-Latch Identification in Reachable State Space

    Publication Year: 2009 , Page(s): 1113 - 1126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1081 KB) |  | HTML iconHTML  

    The large number of latches in current digital designs increases the complexity of formal verification and logic synthesis, since an increase in latch numbers leads to an exponential expansion of the state space. One solution to this problem is to find the functional dependences among these latches. With the information of functional dependences, these latches can be identified as dependent or essential latches, and the state space can be constructed using only the essential latches. Although much research has been devoted to exploring the functional dependences among latches using binary-decision-diagram (BDD)-based symbolic algorithms, this issue is still unresolved for large sequential circuits. In this paper, we propose a heuristic to identify the dependent latches based on the state-of-the-art work. In addition, our proposed approach detects sequential functional dependences existing in the reachable state space only. The sequential functional dependences can identify additional dependent latches after a specific time frame in order to achieve additional reduction of the state space. Experimental results show that this approach can deal with large sequential circuits with up to 9000 latches in a reasonable time while simultaneously identifying their combinational and sequential dependent latches. For instance, with s13207 in ISCAS'89, 23% of the latches are identified as combinational dependent latches, and an additional 13% of the latches are identified as sequential dependent latches. For the reachability analysis of s13207, with the benefits of dependent-latch identification, 70.70% of the BDD size and 73.32% of the CPU time can be reduced within the same time frame. Furthermore, 2890.76% more states can be reached under the 600 000-s run-time limit. View full abstract»

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  • Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering

    Publication Year: 2009 , Page(s): 1127 - 1137
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1183 KB) |  | HTML iconHTML  

    Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and ldquooutput quality.rdquo In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the ldquoless important computationsrdquo are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. View full abstract»

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  • Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems

    Publication Year: 2009 , Page(s): 1138 - 1149
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1125 KB) |  | HTML iconHTML  

    A time-domain orthogonal finite-element reduction-recovery method is developed to overcome the large problem sizes encountered in the simulation of large-scale integrated-circuit and package problems. In this method, a set of orthogonal prism vector basis functions is developed. Based on this set of bases, an arbitrary 3-D multilayered system such as a combined package and die is reduced to a single-layer system with negligible computational cost. More importantly, the reduced single-layer system is diagonal and, hence, can be solved readily. From the solution of the reduced system, the solution of the other unknowns is recovered in linear complexity. The method entails no theoretical approximation. It applies to any arbitrarily shaped multilayer structure involving inhomogeneous materials or any structure that can be geometrically modeled by triangular prism elements. In addition, it permits nonlinear device modeling and broadband simulation within one run. Numerical and experimental results have demonstrated its accuracy and high capacity in simulating on-chip, package, and die-package interface problems. View full abstract»

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  • Convergence of Transverse Waveform Relaxation for the Electrical Analysis of Very Wide Transmission Line Buses

    Publication Year: 2009 , Page(s): 1150 - 1161
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1254 KB) |  | HTML iconHTML  

    In this paper, we study the convergence and approximation error of the transverse waveform relaxation (TWR) method for the analysis of very wide on-chip multiconductor transmission line systems. Significant notational simplicity is achieved in the analysis using a splitting framework for the per-unit-length matrix parameters of the transmission lines. This splitting enables us to show that the state-transition matrix of the coupled lines satisfies a linear Volterra integral equation of the second kind, whose solution is generated by the TWR method as a summable series of iterated kernels with decreasing norms. The upper bounds on these norms are proved to be O(k r/r !), where r is the number of iterations and k is a measure of the electromagnetic couplings between the lines. Very fast convergence is guaranteed in the case of weak coupling (k Lt 1). These favorable convergence properties are illustrated using a test suite of industrial very large scale integration global buses in a modern 65-nm CMOS process, where it is shown that few ( ap 3) Gauss-Jacobi iterations are sufficient for convergence to the exact solution. View full abstract»

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  • Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming

    Publication Year: 2009 , Page(s): 1162 - 1175
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB) |  | HTML iconHTML  

    This paper presents CAFFEINE, a method to automatically generate compact interpretable symbolic performance models of analog circuits with no prior specification of an equation template. CAFFEINE uses SPICE simulation data to model arbitrary nonlinear circuits and circuit characteristics. CAFFEINE expressions are canonical-form functions: product-of-sum layers alternating with sum-of-product layers, as defined by a grammar. Multiobjective genetic programming trades off error with model complexity. On test problems, CAFFEINE models demonstrate lower prediction error than posynomials, splines, neural networks, kriging, and support vector machines. This paper also demonstrates techniques to scale CAFFEINE to larger problems. View full abstract»

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  • Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design

    Publication Year: 2009 , Page(s): 1176 - 1189
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB) |  | HTML iconHTML  

    Circuit reliability under random parametric variation is an area of growing concern. For highly replicated circuits, e.g., static random access memories (SRAMs), a rare statistical event for one circuit may induce a not-so-rare system failure. Existing techniques perform poorly when tasked to generate both efficient sampling and sound statistics for these rare events. Statistical blockade is a novel Monte Carlo technique that allows us to efficiently filter-to block-unwanted samples that are insufficiently rare in the tail distributions we seek. The method synthesizes ideas from data mining and extreme value theory and, for the challenging application of SRAM yield analysis, shows speedups of 10 - 100 times over standard Monte Carlo. View full abstract»

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  • Locality-Driven Parallel Power Grid Optimization

    Publication Year: 2009 , Page(s): 1190 - 1200
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1194 KB) |  | HTML iconHTML  

    Large very large-scale-integration power/ground distribution networks are challenging to analyze and design due to the sheer network complexity. In this paper, a parallel sizing optimization approach is presented to minimize the wiring area of a power grid while meeting IR drop and electromigration constraints. Motivated by a proposed two-level hierarchical optimization, we present a novel locality-driven partitioning scheme to allow for divide-and-conquer-based scalable optimization of large power grids, which is infeasible via flat optimization. Unlike existing partitioning-based strategies, the proposed method is very flexible in terms of choice of partitioning boundaries and sizes. Equally importantly, it allows for simultaneous sizing of multiple partitions, leading itself naturally to parallelization. View full abstract»

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  • A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations

    Publication Year: 2009 , Page(s): 1201 - 1212
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis and optimization has become essential. While statistical timing analysis has an important role to play in this process, it is equally important to develop die-specific delay prediction techniques using postsilicon measurements. We present a novel method for postsilicon delay analysis. We gather data from a small number of on-chip test structures, and combine this information with presilicon statistical timing analysis to obtain narrow die-specific timing probability density function (PDF). Experimental results show that for the benchmark suite being considered, taking all parameter variations into consideration, our approach can obtain a PDF whose standard deviation is 79.0% smaller, on average, than the statistical timing analysis result. The accuracy of the method defined by our metric is 99.6% compared to Monte Carlo simulation. The approach is scalable to smaller test structure overheads and can still produce acceptable results. View full abstract»

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  • System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm

    Publication Year: 2009 , Page(s): 1213 - 1223
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (654 KB) |  | HTML iconHTML  

    Growing complexity in system-on-a-chip (SoC) design demands effective approaches to explore various architectures quickly for the target applications. With the common use of intellectual properties (IPs) in SoC and the large amount of data interchanges among IPs, communication architecture significantly affects the system in terms of power and performance. Therefore, designers should carefully plan the communication architecture to meet the power and performance requirements. While repeatedly performing a power optimization under a performance constraint approach N times seems practical for the power and performance co-exploration, the time required to explore such solutions inevitably increases, since there are numerous performance constraints. This paper presents a pseudo-parallel method for bus architecture exploration at the system level (PBAES) to speedup the power and performance of co-exploration time. PBAES can intelligently search interesting portions of the design space to enhance the efficiency of co-exploration, and share the candidate solutions of each to achieve a more rapid overall exploration. The experimental results indicate that PBAES is 1.6 times to 14 times faster than an approach without the pseudo-parallel method with a generated architecture of similar quality. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression

    Publication Year: 2009 , Page(s): 1224 - 1236
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (447 KB) |  | HTML iconHTML  

    Instruction compression is important in embedded system design since it reduces the code size (memory requirement) and thereby improves the overall area, power, and performance. Existing research in this field has explored two directions: efficient compression with slow decompression, or fast decompression at the cost of compression efficiency. This paper combines the advantages of both approaches by introducing a novel bitstream placement method. Our contribution in this paper is a novel compressed bitstream placement technique to support parallel decompression without sacrificing the compression efficiency. The proposed technique enables splitting a single bitstream (instruction binary) fetched from memory into multiple bitstreams, which are then fed into different decoders. As a result, multiple slow decoders can simultaneously work to produce the effect of high decode bandwidth. We prove that our approach is a close approximation of the optimal placement scheme. Our experimental results demonstrate that our approach can improve the decode bandwidth up to four times with minor impact (less than 3%) on the compression efficiency. View full abstract»

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  • Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints

    Publication Year: 2009 , Page(s): 1237 - 1250
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to alternatives such as tiled silicon and single-level embedded modules as well as 3-D die stacks. Among the various choices, finding an optimal solution for system implementation deals usually with cost, performance, power, thermal, and technological tradeoff analyses at the system conceptual level. It has been estimated that decisions made in the first 20% of the design cycle influence up to 80% of the final product cost. In this paper, we discuss realistic metrics appropriate for performance and cost tradeoff analyses both at the system conceptual level in the early stages of the design cycle and in the implementation phase, for verification. In order to validate the proposed metrics and methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and the performance tradeoffs discussed. This case study is used to highlight the importance of a cost and performance tradeoff analysis early in the design flow. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

    Publication Year: 2009 , Page(s): 1251 - 1264
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (920 KB) |  | HTML iconHTML  

    We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimum-Period Register Binding

    Publication Year: 2009 , Page(s): 1265 - 1269
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    This paper points out that register binding in the high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions often lead to different smallest feasible clock periods. Based on that observation, we formally draw up the problem of register binding for clock-period minimization. Compared with the left edge algorithm, experimental data show that, in most benchmark circuits, our approach can greatly reduce the clock period without any overhead on the number of registers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Process Variation-Aware Test for Resistive Bridges

    Publication Year: 2009 , Page(s): 1269 - 1274
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesized International Symposium on Circuits and Systems benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation

    Publication Year: 2009 , Page(s): 1274 - 1278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (597 KB) |  | HTML iconHTML  

    The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which becomes exacerbated as design complexity increases. An alternative method is static timing analysis (STA), which can drastically reduce analysis time. However, STA sacrifices accuracy for speed and often produces unrealistic results such as false paths and overly pessimistic estimates. In this paper, we propose a hybrid analysis method that can significantly reduce analysis time, while preserving accuracy, with respect to the traditional gate-level simulation. Our key idea is that a large speedup would be possible by removing those events that are repetitious and unnecessary for simulation. In particular, we focus on reducing the number of clock-related events, which account for a major portion of all the events handled by a simulator. We tested the proposed method extensively with various benchmark circuits as well as industrial designs. Our experimental results exhibit that the proposed approach accelerates the total simulation speed by two times on average, yet maintaining the accuracy acquired by the traditional gate-level simulation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Embedded Systems Letters

    Publication Year: 2009 , Page(s): 1279
    Save to Project icon | Request Permissions | PDF file iconPDF (536 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2009 , Page(s): 1280
    Save to Project icon | Request Permissions | PDF file iconPDF (25 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2009 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (27 KB)  
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu