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Electron Devices and Semiconductor Technology, 2009. IEDST '09. 2nd International Workshop on

Date 1-2 June 2009

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Displaying Results 1 - 25 of 49
  • Reliability performance characterization of SOI FinFETs

    Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1874 KB) |  | HTML iconHTML  

    FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages. View full abstract»

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  • A novel approach to overcome bandwidth limitations of parallel computers based on cmos, Part-1 : General concepts

    Page(s): 1 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (510 KB) |  | HTML iconHTML  

    We present a new approach to overcome the well-known deficiency of CMOS technology pertaining to global communication capability within large-scale, parallel information processing systems such as supercomputers, internet switches and multi-ported storage. This is based on a novel surface-normal communication scheme. It exploits massively parallel quantum tunneling through an array of field emission devices lining the surface of an electromagnetic vacuum chamber and multi-trajectory electron optics through the cavity volume. This results in significantly reduced energy loss per bit communicated, due loss-less nature of quantum tunneling and collision-free movement of electrons through vacuum. Modulation of field-emitted electron beams and the new electron optical system are both enabled by recent insights into optimization problems with multiple global minima. Just as many natural systems governed by potential energy functions with multiple global minima are well understood theoretically (e.g. systems with translational symmetry in crystallography and solid state physics), we are able to analyze behavior of electrons in systems with artificially created symmetries based on finite projective geometry. The resulting physical complexity of connecting n information sources to n destinations is O(n), in contrast with conventional approaches of O(n2) physical complexity. View full abstract»

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  • An analytical drain current model for undoped 4-T asymmetric double gate MOSFETs

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1351 KB) |  | HTML iconHTML  

    In this paper, we derive an analytical model of drain current for an Undoped 4-T asymmetric double gate MOSFET based on the solution of the 1D Poisson's equation. The equations are valid for both the subthreshold and superthreshold regime of operation. The current is formulated using the Pao-Sah's double integral method. The model can be used to study the effect of the different gate voltages, gate work functions and the oxide thickness of the front and back gate on the drain current of the undoped DG MOSFET. The results have been verified with a 2D device simulator and a good agreement is obtained. View full abstract»

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  • From millibits to terabits per second and beyond - Over 60 years of innovation

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB) |  | HTML iconHTML  

    Three innovations responsible for an explosive growth in available information bandwidth over the last 30 years are highlighted. These include the invention of the bipolar and MOS transistors, development of information theory and the invention of solid-state lasers. Although demonstrated 13 years later than the bipolar transistors, fundamental contributions that led to rapid adoption of MOS as the technology of choice in meeting the needs of wireless and lightwave communication systems is explained. Continued research in understanding and improving MOSFET noise performance is elucidated. Theoretical basis of ultra-low-noise optical signal detection using finite medium and non-instantaneous multiplication are presented. View full abstract»

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  • Source-drain engineering for Sub-90 nm junction-field-effect transistors

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2026 KB) |  | HTML iconHTML  

    This paper presents sub-90 nm symmetric and asymmetric source-drain junction-field-effect transistor (JFET) devices for ultra-low voltage operation. The JFET devices are suitable for ultra-low voltage analog applications by overcoming the limitations of advanced MOSFET devices and CMOS technologies. However, the performance of sub-90 nm channel-JFETs is limited by higher off-state leakage current and lower ON/OFF current ratio. In this paper, we introduce asymmetric source-drain device architecture to improve the ON/OFF performance of JFET devices. The numerical device simulation results show that the proposed asymmetric devices significantly reduce the off-state leakage current in contrast to the symmetric devices for high performance operation at ultra-low power supply voltage of 0.5 V. View full abstract»

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  • Micromachined piezoelectric acoustic device

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1342 KB) |  | HTML iconHTML  

    Micromachined technology has been widely used to reduce device size and improve performance. In this paper, our research activities on micromachined piezoelectric acoustic devices at wide frequency range, from audio microphones to ultrasonic transducers, are reviewed. These devices are based on ferroelectric thin films, and exceed the conventional acoustic devices in excellent performance, miniaturized size, high reliability and compatibility with conventional integrated circuit fabrication. Resonance frequency can be determined by the thickness of each layer composing the thin film. Compact arrays of these devices are designed, fabricated and characterized to enhance sensitivity and pointing. Micromachined acoustic devices could find extensive applications in practical systems. View full abstract»

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  • Scattering-limited and ballistic transport in nanoelectronic devices

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (537 KB) |  | HTML iconHTML  

    The fundamental processes on nanoscale that may influence the design of nanoelectronic chips, sensors, and systems is presented. The focus is on the breakdown of Ohm's law in nanoscale devices extensively being used to assess the performance of a ldquosystem-on-a-chip,rdquo may it be for bio, chemical, physical or engineering applications. Novel insights on theories of three sources of transformation of Ohm's law are enumerated: quantum confinement in low-dimensional nanostructures, ballistic transport when conducting channel length is smaller than the mean free path, and high-field initiated carrier asymmetric distribution. The saturation velocity arising from the high-field initiated mobility degradation is shown to be the intrinsic velocity that depends on the nanostructure dimensionality, its carrier concentration, and the ambient temperature, in direct contrast to single number that is quoted in the literature. The ballistic intrinsic velocity is the ultimate saturation velocity that can be lowered by the onset of a quantum emission that may be an optical phonon or photon quantum emitted from an excited quantized level to the ground state. The results presented will have profound impact in the interpretation of data on a variety of nanoelectronic devices and systems that may exist with varying low dimensionality, i. e., classical (analogue energy spectrum) in one or more of the three cartesian directions while other directions go quantum (digitized energy spectrum). View full abstract»

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  • Unified compact modeling for Bulk/SOI/FinFET/SiNW MOSFETs

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1665 KB) |  | HTML iconHTML  

    This paper describes seamless transitions among various MOS devices, ranging from bulk and partially/fully-depleted SOI to double-gate FinFETs and silicon-nanowire MOSFETs. The underlying governing equations for various structures are outlined, which provide the motivation for unifying MOS compact models with the unified regional modeling (URM) approach. View full abstract»

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  • Future device scaling - Beyond traditional CMOS

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1578 KB) |  | HTML iconHTML  

    Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore's law. View full abstract»

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  • Integrated CMOS gas sensors

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1411 KB) |  | HTML iconHTML  

    We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated. The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology. The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based on resistance to time period conversion followed by frequency to digital converter. Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range. RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas. View full abstract»

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  • Technology roadmap for 22nm and beyond

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (933 KB) |  | HTML iconHTML  

    Logic CMOS technology roadmap for dasia22 nm and beyondpsila is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Regarding the downsize limit, it would take probably 20 to 30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized. View full abstract»

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  • Recent advances in charge trap flash memories

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    This paper reviews recent advances in Charge Trap Flash (CTF) memories. CTFs are predicted to replace the traditional floating-gate flash devices beyond the 32 nm node. The paper focuses on work done at IIT Bombay in the areas of both nitride-based SONOS devices as well as nanocrystal (NC)-based devices. For SONOS devices, results are presented for optimization of the nitride layer to obtain the best characteristics, and the simulation of the program/erase transients. For NC devices, experimental characteristics of single and dual layer cells, as well as simulation results are presented. View full abstract»

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  • Fully analytical charge sheet model with quantum mechanical effects for short channel MOSFETs

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (415 KB) |  | HTML iconHTML  

    An analytical model for deep submicron MOSFETs based on quantum charge-sheet approximation including the drift-diffusion equation is presented. In this model the surface potential is obtained analytically considering quantum mechanical effects in the inversion region. The field dependent mobility variations, velocity saturation of carriers and secondary effects such as DIBL and channel length modulation have been incorporated in this model, which shows excellent match with experimental data and two-dimensional device simulator results. The model calculates the drain current and the channel conductance accurately for sub-100 nm devices with minimum number of model parameters. View full abstract»

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  • Thermally oxidized LPCVD silicon as gate dielectric on GaN

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (411 KB) |  | HTML iconHTML  

    A two step gate dielectric deposition technique on GaN, viz. thermal oxidation of Low Pressure Chemical Vapor Deposited (LPCVD) silicon is reported. Current-Voltage (I-V) and Capacitance-Voltage (C-V) characterization of the Metal Insulator Semiconductor (MIS) capacitors are carried out to assess the interface properties. MIS devices with thermal oxide show improved I-V characteristics compared to those with Plasma Enhanced Chemical Vapor Deposited (PECVD) SiO2. However, Si deposition and oxidation schedule has to be carefully optimized to achieve high quality SiO2 on GaN. View full abstract»

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  • Numerical investigation of excess RF channel noise in sub-100 nm MOSFETs

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (398 KB) |  | HTML iconHTML  

    High-frequency simulations of channel-thermal noise in MOSFETs with gate-lengths of 40 nm, 80 nm, and 110 nm are presented. The simulated noise parameter gamma is a stronger function of the carrier transport model at shorter gate-lengths. Velocity saturation is necessary to produce a good match between the simulated and measured DC I-V characteristics using either the drift-diffusion or hydrodynamic transport models. However, in the presence of velocity saturation, the simulated noise is insufficient in explaining the observed excess noise. Hence, these physics-based device-level simulations point to the presence of a non-thermal RF noise source in the FET channel. View full abstract»

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  • High-frequency noise measurements on MOSFETs with channel-lengths in sub-100 nm regime

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    High-Frequency signal and noise measurements on 40 nm, 80 nm, and 110 nm, gate-length MOS transistors are performed. On-wafer measurements of S-parameters up to 18 GHz yield an accurate small-signal RF device model with gm in excess of 1000 mS/mm. Noise contributions due to gate resistance, substrate resistance, source and drain resistances, substrate current and induced-gate noise are found to be small in comparison with total observed noise. The noise parameter gamma is bias dependent and increases as channel-length decreases. The observed values are well above the ideal value of 2/3 consistent with previously published results. View full abstract»

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  • SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    Subthreshold region of operation has gained wide research interest for applications requiring Ultra low power consumption and medium frequency of operation. Double gate MOSFETs are proved to be better candidates for subthreshold operation due to their near ideal subthreshold slope and negligible gate capacitance. However it is not yet clear whether symmetric (SDG) or Asymmetric (ADG) DG with options of Tied (3T) and Independent gates (4T) are optimal for subthreshold circuit design. In this paper, we compare the performance characteristics of SDG and ADG circuits with tied (3T) and Independent gate (4T) options for the subthreshold logic by applying them to some basic logic gates such as NAND, NOR gates for the 32 nm technology node. We also present the performance comparisons of SDG and ADG circuits for subthreshold logic in the presence of supply voltage and temperature variations. We found that 3T ADG circuits offer approximately 13-14% better power consumption, 4-5% better speed and 16-18.3% better PDP than 3TSDG based circuits. View full abstract»

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  • Study of charge density at InxGa1-xN/GaN heterostructure interface

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (565 KB) |  | HTML iconHTML  

    Energy-bands in undoped InxGa1-xN/GaN heterostructures have been simulated using 1D Poisson/Schrodinger solver: A Band Diagram Calculator, by self-consistent solution of Schrodinger and Poisson equations. The formation of two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) were observed at the interface of undoped InxGa1-xN/GaN based heterostructures. Charge concentrations throughout the structures were analyzed which show the confinement of charge in a quantum well at the heterointerface. Charge density as a function of depth from surface to substrate has also been presented in this paper. The formation of 2DEG and 2DHG and the dependence of their densities on layer thickness, alloy composition and temperature have been investigated. View full abstract»

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  • Study of random dopant fluctuation effects in fully depleted silicon on insulator MOSFET using analytical model

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (671 KB) |  | HTML iconHTML  

    The effect of random dopant fluctuation in the channel of a fully depleted SOI-MOSFET is investigated using analytical models for threshold voltage and subthreshold current. Analytical models are based on solving 2D Poisson's equation considering non-uniformly doped channel. Since analytical models are faster compared to numerical simulations, a large number of devices can be simulated. View full abstract»

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  • Characterization of RF sputter deposited HfAlOx dielectrics for MIM capacitor applications

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (589 KB) |  | HTML iconHTML  

    Advanced metal-insulator-metal (MIM) capacitors with ultra-thin (EOT~2.1-4.9 nm) RF sputter-deposited HfAlOx dielectric layers having excellent electrical properties have been fabricated. The capacitance density is found to increase with the decrease in thickness of insulator film. MIM capacitors show little voltage and frequency dependence along with low dissipation and leakage current. Our experimental observations indicate the high potential of HfAlOx for MIM capacitor applications. View full abstract»

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  • Novel hybrid CMOS and CNFET inverting amplifier design for area, power and performance optimization

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3074 KB) |  | HTML iconHTML  

    There is a pressing need to explore circuit design ideas in new emerging technologies in deep-submicron in order to exploit their full potential during the early stages of their development. Carbon nanotube based technology (CNT) has significant potential to replace silicon technology sometimes in the future. This paper presents an optimal design of hybrid CMOS and carbon nanotube field effect transistor (CNFET) based complementary type inverting amplifier for area-power-performance optimization in terms of operating voltage, number of nanotubes, diameter and pitch of the CNFET along with the qualitative explanation of the obtained results at an operating voltage of 0.9 V using HSPICE simulations. Furthermore, comparison of hybrid technology amplifiers with planar CMOS at the 32 nm technology node showed that the performance of PMOS-NCNFET configuration is better in terms of Gain (62% higher), GBP (fT, 181% higher), slew rate (163% higher) etc. while PCNFET-NMOS outperforms in terms of Gain (59% higher), Bandwidth (332% higher), GBP (395%), Output resistance (328% lower) for typical load capacitance (CL = 1fF) at the cost of higher power consumption. View full abstract»

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  • Influence of SiN composition on program and erase characteristics of SANOS-type flash memories

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1254 KB) |  | HTML iconHTML  

    Composition of the silicon-nitride charge trap layer strongly impacts electron and hole trap properties. This significantly impacts charge trap flash memory performance and reliability. Important trade-offs between program/erase (P/E) levels (memory window) and retention loss is shown and critical trends identified. Increasing the Si-richness of the SiN layer improves memory window by increasing erase efficiency. E-state retention characteristics are improved but at the expense of higher P-state retention loss. View full abstract»

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  • Surface plasmon polaritons in nano-waveguides with semiconductor guiding layer

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1248 KB) |  | HTML iconHTML  

    Surface plasmon propagation in nano scaled waveguide containing a semiconductor film embedded in dielectric media is studied in this paper. The analytical dispersion relation is reached for the symmetric and antisymmetric mode. The propagation characteristics is analyzed for various material and structural parameters. As an application to integrated waveguide elements, a garnet layer bonded on semiconductor-on-insulator waveguide structure, is considered. The nonreciprocal phase shift as a function of the propagating semiconductor layer thickness at different wavelengths is also studied. View full abstract»

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  • Optimization of hetero junction n-channel tunnel FET with high-k spacers

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    Use of high-k spacers to boost the ON state current of SiGe-Si hetero junction tunnel FETs is proposed for the first time. Extensive device simulations have been conducted to understand the device physics. It is shown that the fringing fields through the spacer enhances the ON state current without modifying the OFF state current or the subthreshold swing. The spacer k can be traded off against the Ge mole fraction in SiGe. It is shown that the OFF state current can be further reduced by employing a drain side overlap in combination with the high-k spacer. Device designs that satisfy the ITRS requirements for 20 nm gate length technology for HP, LOP and LSTP applications are proposed using Ge mole fraction of 0.4 to 0.48 in SiGe and spacer k of 14, which can be integrated with presently available technologies. View full abstract»

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  • Nonvolatile unipolar memristive switching mechanism of pulse laser ablated NiO films

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (445 KB) |  | HTML iconHTML  

    Memristive unipolar switching characteristics of PLD grown NiO films have been investigated for nonvolatile memory applications. Grazing incidence XRD study reveals the polycrystalline behavior of NiO films. AFM topography shows a smooth surface of NiO having RMS roughness ~ 3.0 nm. By applying a proper voltage bias and compliance, Pt/NiO/Pt structures exhibited unipolar resistive switching from one state to the other state. The device is found to be switched ON and OFF at a very low voltage. This resistive switching behavior is reproducible and the ratio between the high resistance and low resistance states can be as high as orders of 102. The switching phenomena have been explained using the rupture and formation mechanisms of conducting filaments. View full abstract»

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