IEEE Micro

Issue 3 • May-June 2009

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Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • [Front cover]

    Publication Year: 2009, Page(s): c2
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  • [Advertisement]

    Publication Year: 2009, Page(s): 1
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  • Contents

    Publication Year: 2009, Page(s):2 - 3
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  • The Revolution in Spectrum Allocation

    Publication Year: 2009, Page(s):4 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (8291 KB) | HTML iconHTML

    At the end of 2007 (the latest data) the US Federal Communications Commission estimates there were 263 million wireless subscribers (almost 2.3 subscriptions per household in the US). Subscribers used an average of 769 minutes per month, generating US$0.06 average revenue per minute for all traffic ($0.05 for voice traffic). The FCC also estimates that 14.5 percent of US households received their ... View full abstract»

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  • Embedded Multicore Processors and Systems

    Publication Year: 2009, Page(s):7 - 9
    Cited by:  Papers (13)
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  • Maintaining I/O Data Coherence in Embedded Multicore Systems

    Publication Year: 2009, Page(s):10 - 19
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1211 KB) | HTML iconHTML

    In embedded systems, multiple cores mean multiple caches and often multiple cache levels. Consequently, maintaining coherency between the cores' caches and the data generated or consumed by I/O devices is challenging, with different solutions trading off hardware versus software complexity. The optimal approach for I/O data coherence depends on application and system characteristics, and might req... View full abstract»

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  • Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

    Publication Year: 2009, Page(s):20 - 30
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1132 KB) | HTML iconHTML

    DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating. View full abstract»

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  • MPA: Parallelizing an Application onto a Multicore Platform Made Easy

    Publication Year: 2009, Page(s):31 - 39
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1145 KB) | HTML iconHTML

    Commercial multicore platforms offer flexibility, computational power, and energy efficiency. However, a key open issue remains: how can designers quickly and efficiently map an application onto such a platform while profiting from the potential benefits? This article presents a tool to parallelize applications for execution on embedded multicore platforms, allowing fast design space exploration. View full abstract»

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  • Software Standards for the Multicore Era

    Publication Year: 2009, Page(s):40 - 51
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1845 KB) | HTML iconHTML

    Systems architects commonly use multiple cores to improve system performance. Unfortunately, multicore hardware is evolving faster than software technologies. New multicore software standards are necessary in light of the new challenges and capabilities that embedded multicore systems provide. The newly released multicore communications API standard targets small-footprint, highly efficient interc... View full abstract»

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  • Memory Subsystems in High-End Routers

    Publication Year: 2009, Page(s):52 - 63
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (868 KB) | HTML iconHTML

    As Internet routers scale to support next-generation networks, their memory subsystems must also scale. Several solutions combine static RAM and dynamic RAM buffering but still have major scaling limitations. Using a parallel architecture and distributed memory-management algorithms with hybrid SRAM/DRAM improves buffering performance. The parallel hybrid SRAM/DRAM memory system is also work conse... View full abstract»

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  • Software Architects [review of 97 Things Every Software Architect Should Know: Collective Wisdom from the Experts (Monson-Haefel, R., Ed.; 2009)]

    Publication Year: 2009, Page(s):62 - 64
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  • [Advertisement - Back cover]

    Publication Year: 2009, Page(s): c3
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    Publication Year: 2009, Page(s): c4
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IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center