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Computer Architecture Letters

Issue 1 • Date Jan. 2009

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Displaying Results 1 - 15 of 15
  • [Front cover]

    Publication Year: 2009 , Page(s): c1
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  • Editorial Board [Cover2]

    Publication Year: 2009 , Page(s): c2
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  • Weighted Random Routing on Torus Networks

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (125 KB) |  | HTML iconHTML  

    In this paper, we introduce a new closed-form oblivious routing algorithm called W2TURN that is worst-case throughput optimal for 2D-torus networks. W2TURN is based on a weighted random selection of paths that contain at most two turns. In terms of average hop count, W2TURN outperforms the best previously known closed-form worst-case throughput optimal routing algorithm called IVAL. In addition, w... View full abstract»

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  • Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs

    Publication Year: 2009 , Page(s): 5 - 8
    Cited by:  Papers (9)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    Demand for memory capacity and bandwidth keeps increasing rapidly in modern computer systems, and memory power consumption is becoming a considerable portion of the system power budget. However, the current DDR DIMM standard is not well suited to effectively serve CMP memory requests from both a power and performance perspective. We propose a new memory module called a multicore DIMM, where DRAM c... View full abstract»

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  • A Predictive Shutdown Technique for GPU Shader Processors

    Publication Year: 2009 , Page(s): 9 - 12
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    As technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low-power GPU (graphics processing unit) focus on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage/Frequency Scaling) and clock gating. In this paper, we explore the potential of adopting architecture-level power gating techniques for leakage reduction on GPU. In par... View full abstract»

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  • An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators

    Publication Year: 2009 , Page(s): 13 - 16
    Request Permissions | Click to expandAbstract | PDF file iconPDF (106 KB) |  | HTML iconHTML  

    Computer architecture simulation has always played a pivotal role in continuous innovation of computers. However, constructing or modifying a high quality simulator is time consuming and error-prone. Thus, often architecture description languages (ADLs) are used to provide an abstraction layer for describing the computer architecture and automatically generating corresponding simulators. Along the... View full abstract»

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  • CPU Accounting in CMP Processors

    Publication Year: 2009 , Page(s): 17 - 20
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (138 KB) |  | HTML iconHTML  

    Chip-multiprocessor (CMP) architectures introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the process scheduli... View full abstract»

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  • A High-Throughput Distributed Shared-Buffer NoC Router

    Publication Year: 2009 , Page(s): 21 - 24
    Cited by:  Papers (6)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (158 KB) |  | HTML iconHTML  

    Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or an output-buffered router (OBR). OBRs are attractive because they have higher throughput and lower queuing delays under high loads than IBRs. Howev... View full abstract»

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  • Many-Core vs. Many-Thread Machines: Stay Away From the Valley

    Publication Year: 2009 , Page(s): 25 - 28
    Cited by:  Papers (17)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (121 KB) |  | HTML iconHTML  

    We study the tradeoffs between many-core machines like Intelpsilas Larrabee and many-thread machines like Nvidia and AMD GPGPUs. We define a unified model describing a superposition of the two architectures, and use it to identify operation zones for which each machine is more suitable. Moreover, we identify an intermediate zone in which both machines deliver inferior performance. We study the sha... View full abstract»

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  • Architecture Independent Characterization of Embedded Java Workloads

    Publication Year: 2009 , Page(s): 29 - 32
    Request Permissions | Click to expandAbstract | PDF file iconPDF (95 KB) |  | HTML iconHTML  

    This paper presents architecture independent characterization of embedded Java workloads based on the industry standard GrinderBench benchmark which includes different classes of real world embedded Java applications. This work is based on a custom built embedded Java virtual machine (JVM) simulator specifically designed for embedded JVM modeling and embodies domain specific details such as thread... View full abstract»

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  • A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network"

    Publication Year: 2009 , Page(s): 33 - 34
    Request Permissions | Click to expandAbstract | PDF file iconPDF (63 KB) |  | HTML iconHTML  

    A recent work proposed to simplify fat-trees with adaptive routing by means of a load-balancing deterministic routing algorithm. The resultant network has performance figures comparable to the more complex adaptive routing fat-trees when packets need to be delivered in order. In a second work by the same authors published in IEEE CAL, they propose to simplify the fat-tree to a unidirectional multi... View full abstract»

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  • Ad - IEEE Computer Society Digital Library

    Publication Year: 2009 , Page(s): 36
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    Publication Year: 2009 , Page(s): 35
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  • Information for authors

    Publication Year: 2009 , Page(s): c3
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  • IEEE Computer Society [Cover4]

    Publication Year: 2009 , Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
José Martinez
Cornell University
336 Frank H.T. Rhodes Hall
Ithaca, NY 14853 USA
e-mail: martinez@cornell.edu