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Circuits, Devices and Systems, IEE Proceedings G

Issue 1 • Date Feb 1993

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Displaying Results 1 - 11 of 11
  • Symbolic analysis of electronic circuits based on a tree enumeration technique

    Page(s): 68 - 74
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    A topological method for symbolic analysis of electronic circuits is presented. The method is based on the derivation of the tree products of unistor graphs. A straightforward procedure to produce all directed trees of a unistor graph in independent groups is given. The network cofactor is obtained by calculating the network determinant of a modified unistor graph. A computer program based on the given method written for PCs is also described View full abstract»

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  • Systolic realisation of delayed two-path linear phase FIR digital filters

    Page(s): 75 - 80
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A new method for high speed realisation of 1-dimensional (1D) linear phase FIR digital filter is presented. The method makes use of pipelining in systolic arrays to reduce the minimum clock cycle time, the delayed two-path structure to increase processing speed, and the symmetry of coefficients in a linear phase FIR digital filter to reduce multiplications. The resultant systolic delayed two-path digital filter structure is consisted of four systolic arrays built from one type of basic cells with nearest neighbour interconnections. The method is optimal in terms of the number of multiplications. Both input and output of the proposed filter structure can also be systolised to form an overall pure systolic structure. The proposed digital filter structure can provide a speed improvement of 32 times as compared to that of a direct realisation of the same filter using a single processor. The proposed method is attractive for high speed adaptive and nonadaptive digital filtering View full abstract»

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  • Unified small-signal-noise model for active microwave devices

    Page(s): 55 - 60
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    A new method for modelling, concurrently, the small-signal and the noise performance of active microwave devices is proposed. Here the determination of the element values in a device equivalent circuit is no longer dependent only on the scattering parameters, but also on the device noise parameters. In other words, the device noise performance is treated as an intrinsic set of characteristics of a device like the S-parameters themselves and influences the determination of element values in the device equivalent circuit. On using the concurrent modelling procedure suggested in this paper, it has been found that, not only can the small-signal performance be simulated accurately, but also the prediction of noise performance is in much better agreement with measurements than those of recent published models View full abstract»

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  • Implementation of real coefficient two-dimensional denominator-separable digital filters based on decomposition techniques

    Page(s): 23 - 32
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    In the paper, the implementation of two-dimensional digital filters is dealt with for the processing of real sequences. The approach is based on decomposition techniques to obtain separable one-dimensional polynomials from a two-dimensional polynomial, and then one-dimensional techniques are used to express the one-dimensional transfer functions as a sum of two reduced-order transfer functions with complex coefficients. Thus, new realisation structures are obtained for the equivalent reduced-order complex-coefficient transfer functions for the processing of real sequences. The authors concentrate more on two-dimensional denominator-separable digital filters and also confine themselves to the parallel-form structures as the emphasis is now on low data throughput delay and high parallelism due to recent advances in VLSI technology. All these structures consist only of one-dimensional first-order minimum-norm sections. Thus, these structures possess low roundoff noise and freedom from overflow limit cycles. A comparison of different structures is made based on data throughput delay, efficiency in multiprocessor environment and roundoff noise properties View full abstract»

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  • Analytical DC model for p-type QW-HEMTs for CAD applications

    Page(s): 7 - 15
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    An analytical charge control model for p-type insulated-gate inverted-structure high electron mobility transistors (I2-HEMTs) and double heterojunction high electron mobility transistors (DH-HEMTs) has been developed. In this model the quasitriangular potential well approximation is used to relate the top-heterojunction Fermi potential to the two-dimensional hole gas (2DHG) concentration inside the quantum well. Based on this charge-control model, an accurate DC current-voltage relationship is obtained. The results from this model are found to be in agreement with the experimental results View full abstract»

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  • Two-segment bistability and basin structure in three-segment PWL circuits

    Page(s): 61 - 67
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    Of all the piecewise-linear circuits known so far which exhibit two stable states, it is typical that their resistor characteristics each have at least three segments. The authors show that bistability cannot be achieved via a two-segment characteristic in the plane. On the other hand, complicated bistable behaviour, including chaotic attractors, can occur locally at the boundary of two linear regions in higher-dimensional circuits. By using a three-segment characteristic, at least three attractors can be generated in the planar Lienard oscillator and five attractors are exhibited in three-dimensional Chua's circuit. Basin structure of the corresponding attractors is examined using numerical simulations. The use of basin delineation in the triggering of multistable circuits is shown View full abstract»

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  • Double and triple charge pump for power IC: ideal dynamical models to an optimised design

    Page(s): 33 - 38
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The authors propose an optimised design methodology for the double and triple optimised charge pump. The circuits discussed give an output voltage greater than the supply voltage and are commonly used in power IC or memory to allow the switching on of a MOS device. The theoretical models of charge pumps in the transient region are reported to obtain better knowledge of the circuits and the optimised design View full abstract»

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  • Adaptive filtering incorporating a local mean estimation substructure

    Page(s): 16 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    Adaptive filters have been used successfully in many applications of signal processing. However, their performance in dealing with signals of nonzero mean, especially with sharp changes (edges), is problematic, which limits the extension of the use of adaptive filters in some important application areas. To overcome this problem, the authors introduce in this paper a scheme for adaptive filtering obtained by incorporating a local mean estimation substructure (denoted as AF-LME scheme). It is shown by theoretical analysis that, by handling the signal mean and the zero mean component (the residual signal) separately, the performance of adaptive algorithms (e.g. the LMS or the RLS) can be improved. Analysis is also given to show the weakness of an adaptive filter in dealing with the edges of the signal mean. This weakness can be overcome by incorporating the technique of low-pass filtering with an edge preserving property as the local mean substructure. A method for the implementation of this substructure is proposed. This implementation was satisfactorily used in computer simulations and representative examples simulations are presented View full abstract»

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  • Nonlinear circuit applications with current conveyors

    Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    Integrable nonlinear building blocks such as multipliers, dividers, and piecewise linear approximation circuits using current conveyors are presented. Several practical circuits including an amplitude modulator, a squarer, a square rooter, and nonlinear resistors also have been demonstrated experimentally. The results presented in the paper will facilitate realisations of nonlinear circuits using CCIIs View full abstract»

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  • Event-driven incremental timing fault simulator

    Page(s): 45 - 54
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    In this paper, FMOTA, an efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC, is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multiprocessor system View full abstract»

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  • IDDQ testing of oscillating bridging faults in CMOS combinational circuits

    Page(s): 39 - 44
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    IDDQ testing has been shown to be an efficient way to test CMOS technology circuits when realistic failures, bridges among others, are considered. A particular group of bridging faults cause the circuit to oscillate because of unstable feedback. The authors focus on the evaluation of IDDQ testability for these bridging faults. An electrical circuit model allows the analytic derivation of characteristics of the oscillating IDD behaviour. it is shown that oscillating faults are testable by classical IDDQ sensors. The knowledge of the ripple frequency and the maximum and minimum values of the oscillating IDD current allows the characterisation of the IDDQ levels, and it is useful in the design of choice of a current sensor in the general case View full abstract»

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