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Computers, IEEE Transactions on

Issue 9 • Date Sept. 1987

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 1987, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1987, Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1987, Page(s): nil1
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  • Efficient Embeddings of Binary Trees in VLSI Arrays

    Publication Year: 1987, Page(s):1009 - 1018
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2228 KB)

    We consider the problem of embedding a complete binary tree in squareor hexagonally-connected VLSI arrays Of processing elements (PE's). This problem can be solved in a radically different manner from current layout techniques which are aimed at laying out a given graph in the plane. The difference is due to the fact that a PE can be used both as a tree node and as a connecting element between dis... View full abstract»

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  • The Effect of Operation Scheduling on the Performance of a Data Flow Computer

    Publication Year: 1987, Page(s):1019 - 1029
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2964 KB)

    The effect of incorporating a priority scheme into a data flow computer is studied in this paper. Specifically, we deal with the scheduling of instructions in a data flow program, and the mechanisms by which such scheduling may be implemented within a data flow computer. We show that the assignment of priorities to data flow operations is a special case of a problem in scheduling theory, and also ... View full abstract»

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  • Processor Tradeoffs in Distributed Real-Time Systems

    Publication Year: 1987, Page(s):1030 - 1040
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2485 KB)

    Optimizing the design of real-time distributed systems is important since the systems are frequently critical to life. This optimization is a difficult problem, and heuristics and designer judgment are called for in the process. The chief cause of the difficulty is the large number of parameters under the designer's control which impact performance and life-cycle cost. We study the interplay betwe... View full abstract»

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  • Performance Models of Timestamp-Ordering Concurrency Control Algorithms in Distributed Databases

    Publication Year: 1987, Page(s):1041 - 1051
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2495 KB)

    A distributed database (DDB) consists of copies of data files (usually redundant) geographically distributed and managed on a computer network. One important problem in DDB research is that of concurrency control. This paper develops a performance model of timestamp-ordering concurrency control algorithms in a DDB. The performance model consists of five components: input data collection, transacti... View full abstract»

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  • On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems

    Publication Year: 1987, Page(s):1052 - 1062
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2088 KB)

    The objective of fault-tolerant computing systems is to provide an error-free operation in the presence of faults. The system has to recover from the effects of a fault by employing certain recovery procedures like program rollback, reload, and restart, etc. However, these recovery procedures, result in interruptions in the system's operation, thus reducing the availability of the system for user ... View full abstract»

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  • Line (Block) Size Choice for CPU Cache Memories

    Publication Year: 1987, Page(s):1063 - 1075
    Cited by:  Papers (82)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3154 KB)

    The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, we study the factors that relate to the selection of a cache line size. Our primary focus is on the cache miss ratio, but we also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc. The behavior of the cache miss ratio as a function... View full abstract»

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  • New Methods for Realizing Plural Near-Native Performance Virtual Machines

    Publication Year: 1987, Page(s):1076 - 1087
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3044 KB)

    This paper presents methods for increasing the efficiency of operating systems in plural virtual machines to a near-native performance level. The proposed direct execution methods support direct I/O execution for plural virtual machines, that is, the V = R virtual machine, and the V = Resi virtual machines, including both I/O instruction issuances and I/O interrupts. All V = Resi virtual machines ... View full abstract»

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  • Implementation and Test of the ACRITH Facility in a System/370

    Publication Year: 1987, Page(s):1088 - 1096
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2366 KB)

    This paper covers some key aspects of the implementation and testing of the ACRITH (``High-Accuracy Arithmetic'') facility in the IBM 4361. It also includes a brief description of its definition in the IBM System/370 Architecture RPQ (IBM Publication SA22-7093). The ACRITH facility consists of five new floating-point operations with controlled rounding. Besides the four basic operations (+, ¿, *,... View full abstract»

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  • Testing Programmable Logic Arrays by Sum of Syndromes

    Publication Year: 1987, Page(s):1097 - 1101
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1230 KB)

    Syndrome testing is a simple and effective fault detection technique applicable to many general circuits. It is particularly useful in two-level circuits, such as programmable logic arrays (PLA's). For a multiple-output network, like PLA's, existing methods test the individual syndromes for each function, where a fault should be detectable in at least one output. This paper shows that the weighted... View full abstract»

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  • A Study of Data Interlock in Computational Networks for Sparse Matrix Multiplication

    Publication Year: 1987, Page(s):1101 - 1107
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1449 KB)

    The general question addressed in this study is: are regular networks suitable for sparse matrix computations? More specifically, we consider a special purpose self-timed computational array that is designed for a specific dense matrix computation. We add to each cell in the network the capability of recognizing and skipping operations that involve zero operands, and then ask how efficient is this... View full abstract»

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  • Successively Improving Bounds on Performance Measures for Single Class Product Form Queueing Networks

    Publication Year: 1987, Page(s):1107 - 1112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    The use of queueing network models to analyze the performance of computer systems is widespread. Typically the analysis requires certain assumptions to be made. Even under such assumptions, the exact analysis of these models for the performance measures could be quite time consuming, especially when various alternate configurations of the system are to be evaluated. In some situations, bounds on t... View full abstract»

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  • Constructing Test Cases for Partitioning Heuristics

    Publication Year: 1987, Page(s):1112 - 1114
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB)

    In analyzing the effectiveness of min-cut partitioning heuristics, we are faced with the task of constructing ``random'' looking test networks with a prescribed cut-set size in its optimal partition. We present a technique for constructing networks over a given set of components that has been a priori partitioned into two parts. The networks have the property that the optimal partition, i.e., one ... View full abstract»

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  • Self-Adjusting Networks for VLSI Simulation

    Publication Year: 1987, Page(s):1114 - 1120
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1333 KB)

    Magnitude networks [1l, [2] have been used as a theoretical base for switch-level simulation of MOS VLSI circuits. We address in this paper the particular problem of evaluating the influence of switches in unknown state on the steady-state response of the network. A two-pass procedure based on local controllers attached to such switches is described and a hardware implementation is proposed which ... View full abstract»

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  • A Note on Strongly Fault-Secure Sequential Circuits

    Publication Year: 1987, Page(s):1121 - 1123
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (722 KB)

    It is proved that any sequential circuit with its next-state function d and output function w is strongly fault secure for unidirectional faults in d and w if i) the outputs of w are encoded in an unordered code, and ii) d and w are implemented with inverter-free circuits. View full abstract»

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  • MOS Test Pattern Generation Using Path Algebras

    Publication Year: 1987, Page(s):1123 - 1128
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1316 KB)

    There is extensive evidence that the classical, stuck-at fault model, operating at the gate level, is inadequate for testing MOS VLSI circuits. By contrast, a ``nonclassical,'' switch-level model¿directly representing open and short circuits in the interconnect and transistors stuck-open or stuck-on¿allows important effects such as MOSFET bidirectionality and tristate behavior to be taken into a... View full abstract»

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  • Performance Analysis of a Multiprocessor-Based Packet Switch in Networks with Link-Level Sliding-Window Flow Control

    Publication Year: 1987, Page(s):1128 - 1132
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1119 KB)

    In the literature, performance studies on packet switches and link-level flow control procedures were treated separately. In this paper, we use a queueing network approach to analyze packet switch performance in terms of the combined effects of switch architectures and link-level flow-control procedures. Results of the study provide us with valuable insights about switch designs and unfold the rel... View full abstract»

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  • Binary Search Revisited: Another Advantage of Fibonacci Search

    Publication Year: 1987, Page(s):1132 - 1135
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (822 KB)

    Binary search method is a well-known and a fundamental technique to search a key out of an ordered table. Fibonacci serh is kind of binary search adopting nonequal splitting criterion for dividing the remaining part of the table. This paper clarifies another advantage of Fibonacci search, which has not been found so far. First, it is shown that, from the viewpoint of the amount of head movement, F... View full abstract»

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  • Correction to ``The Fast Hartley Transform Algorithm''

    Publication Year: 1987, Page(s):1135 - 1136
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  • IEEE Computer Society Publications

    Publication Year: 1987, Page(s): nil2
    Request permission for commercial reuse | PDF file iconPDF (175 KB)
    Freely Available from IEEE
  • [Front cover]

    Publication Year: 1987, Page(s): c2
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    Freely Available from IEEE

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org