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Computers, IEEE Transactions on

Issue 9 • Date Sept. 1987

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 1987 , Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1987 , Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1987 , Page(s): nil1
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  • Efficient Embeddings of Binary Trees in VLSI Arrays

    Publication Year: 1987 , Page(s): 1009 - 1018
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2228 KB)  

    We consider the problem of embedding a complete binary tree in squareor hexagonally-connected VLSI arrays Of processing elements (PE's). This problem can be solved in a radically different manner from current layout techniques which are aimed at laying out a given graph in the plane. The difference is due to the fact that a PE can be used both as a tree node and as a connecting element between distant nodes. New embedding schemes are presented in which (asymptotically) 100 percent of the PE's are utilized as tree nodes. This is a significant savings over known schemes, which achieve 50 percent utilization (the well-known H-tree) and 71 percent for some hexagonal schemes. These schemes also speed up signal propagation from the root to the leaves. View full abstract»

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  • The Effect of Operation Scheduling on the Performance of a Data Flow Computer

    Publication Year: 1987 , Page(s): 1019 - 1029
    Cited by:  Papers (19)  |  Patents (1)
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    The effect of incorporating a priority scheme into a data flow computer is studied in this paper. Specifically, we deal with the scheduling of instructions in a data flow program, and the mechanisms by which such scheduling may be implemented within a data flow computer. We show that the assignment of priorities to data flow operations is a special case of a problem in scheduling theory, and also belongs to the NP-complete class of problems. Therefore, we develop a heuristic approach, based on the well-known Critical Path algorithm, as a basis for determining instruction priorities. Our conclusions, based on the simulation of programs executed in a modified data flow computer, show that adding a priority mechanism is not justifiable in the general case. This is due mostly to the inability to reach the potential improvement offered by scheduling operations, because of implementation restrictions. Nevertheless, certain algorithms (e. g., DFT) can still benefit from the proposed scheme, mainly because of their highly regular, static structure. View full abstract»

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  • Processor Tradeoffs in Distributed Real-Time Systems

    Publication Year: 1987 , Page(s): 1030 - 1040
    Cited by:  Papers (6)
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    Optimizing the design of real-time distributed systems is important since the systems are frequently critical to life. This optimization is a difficult problem, and heuristics and designer judgment are called for in the process. The chief cause of the difficulty is the large number of parameters under the designer's control which impact performance and life-cycle cost. We study the interplay between the more important parameters in this paper using two objective measures, i. e., the mean cost and the probability of dynamic failure in [6], [10]. Among these are the processor burn-in time and processor replacement policy. A central feature of this work is a look at how the application requirements affect the optimality of the distributed systems; indeed, the application requirements are an integral part of the analysis. View full abstract»

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  • Performance Models of Timestamp-Ordering Concurrency Control Algorithms in Distributed Databases

    Publication Year: 1987 , Page(s): 1041 - 1051
    Cited by:  Papers (8)
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    A distributed database (DDB) consists of copies of data files (usually redundant) geographically distributed and managed on a computer network. One important problem in DDB research is that of concurrency control. This paper develops a performance model of timestamp-ordering concurrency control algorithms in a DDB. The performance model consists of five components: input data collection, transaction processing model, communication subnetwork model, conflict model, and performance measures estimation. In this paper we describe the conflict model in detail. We first determine the probability of transaction restarts, the probability of transaction blocking, and the delay due to blocking for the basic timestamp-ordering algorithm. We then develop conflict models for variations of the basic algorithm. These conflict models are illustrated by numerical examples. View full abstract»

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  • On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems

    Publication Year: 1987 , Page(s): 1052 - 1062
    Cited by:  Papers (9)
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    The objective of fault-tolerant computing systems is to provide an error-free operation in the presence of faults. The system has to recover from the effects of a fault by employing certain recovery procedures like program rollback, reload, and restart, etc. However, these recovery procedures, result in interruptions in the system's operation, thus reducing the availability of the system for user applications. Fault-tolerant systems for critical applications include, therefore, standby spares that are ready to replace active modules which fail to recover from the effects of a fault. A standby spare may also be used to replace a module suffering from frequent fault occurrences resulting in too many repetitions of the recovery process, in order to increase the availability of the system for user applications. In this case a module switching policy is needed indicating upon a fault occurrence, whether to retry a failing module or switch it out and replace it by a spare, considering the remaining mission time and the probability of a system crash. A module switching policy for dynamic redundancy systems is presented in this paper and the improvement in application-oriented availability due to the use of this policy is illustrated. View full abstract»

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  • Line (Block) Size Choice for CPU Cache Memories

    Publication Year: 1987 , Page(s): 1063 - 1075
    Cited by:  Papers (80)  |  Patents (1)
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    The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, we study the factors that relate to the selection of a cache line size. Our primary focus is on the cache miss ratio, but we also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc. The behavior of the cache miss ratio as a function of line size is examined carefully through the use of trace driven simulation, using 27 traces from five different machine architectures. The change in cache miss ratio as the line size varies is found to be relatively stable across workloads, and tables of this function are presented for instruction caches, data caches, and unified caches. An empirical mathematical fit is obtained. This function is used to extend previously published design target miss ratios to cover line sizes from 4 to 128 bytes and cache sizes from 32 bytes to 32K bytes; design target miss ratios are to be used to guide new machine designs. Mean delays per memory reference and memory (bus) traffic rates are computed as a function of line and cache size, and memory access time parameters. We find that for high performance microprocessor designs, line sizes in the range 16-64 bytes seem best; shorter line sizes yield high delays due to memory latency, although they reduce memory traffic somewhat. Longer line sizes are suitable for mainframes because of the higher bandwidth to main memory. View full abstract»

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  • New Methods for Realizing Plural Near-Native Performance Virtual Machines

    Publication Year: 1987 , Page(s): 1076 - 1087
    Cited by:  Papers (3)
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    This paper presents methods for increasing the efficiency of operating systems in plural virtual machines to a near-native performance level. The proposed direct execution methods support direct I/O execution for plural virtual machines, that is, the V = R virtual machine, and the V = Resi virtual machines, including both I/O instruction issuances and I/O interrupts. All V = Resi virtual machines have an entirely resident memory and their real addresses are translated into those of the host simply by adding a constant, ¿(¿ 0), which constitutes a starting address given to each V = Resi virtual machine. The V = R virtual machine has almost the same memory attribute as the V = Resi VM except for ¿ = 0. Only one V = R virtual machine can be present in all virtual machines. The experimental results obtained confirm that a near-native performance level, that is, a level exceeding 90 percent of native performance, can be realized for the V = R virtual machine as well as for the V = Resi virtual machines. View full abstract»

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  • Implementation and Test of the ACRITH Facility in a System/370

    Publication Year: 1987 , Page(s): 1088 - 1096
    Cited by:  Papers (3)
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    This paper covers some key aspects of the implementation and testing of the ACRITH (``High-Accuracy Arithmetic'') facility in the IBM 4361. It also includes a brief description of its definition in the IBM System/370 Architecture RPQ (IBM Publication SA22-7093). The ACRITH facility consists of five new floating-point operations with controlled rounding. Besides the four basic operations (+, ¿, *, /) the scalar product of two vectors has been architectured. The theory and many details of this paper are neither bound to IBM System/370 architecture nor to hexadecimal number systems. They apply also to other architectures, for example binary or decimal. View full abstract»

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  • Testing Programmable Logic Arrays by Sum of Syndromes

    Publication Year: 1987 , Page(s): 1097 - 1101
    Cited by:  Papers (11)
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    Syndrome testing is a simple and effective fault detection technique applicable to many general circuits. It is particularly useful in two-level circuits, such as programmable logic arrays (PLA's). For a multiple-output network, like PLA's, existing methods test the individual syndromes for each function, where a fault should be detectable in at least one output. This paper shows that the weighted sum of syndromes of all the outputs covers all single stuck-at-faults, bridging faults, and cross-point faults. Primary input faults are also covered except in one special case which requires some preventive design for testability. This results in the use of one test to cover all single faults. View full abstract»

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  • A Study of Data Interlock in Computational Networks for Sparse Matrix Multiplication

    Publication Year: 1987 , Page(s): 1101 - 1107
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    The general question addressed in this study is: are regular networks suitable for sparse matrix computations? More specifically, we consider a special purpose self-timed computational array that is designed for a specific dense matrix computation. We add to each cell in the network the capability of recognizing and skipping operations that involve zero operands, and then ask how efficient is this resulting network for sparse matrix computation? In order to answer this question, it is necessary to study the effect of data interlock on the performance of self-timed networks. For this, the class of pseudosystolic networks is introduced as a hybrid class between systolic and self-timed networks. Networks in this class are easy to analyze, and provide a means for the study of the worst case performance of self-timed networks. The well known concept of computation fronts is also generalized to include irregular flow of data, and a technique based on the propagation of such computation fronts is suggested for the estimation of the processing time and the communication time of pseudosystolic networks. View full abstract»

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  • Successively Improving Bounds on Performance Measures for Single Class Product Form Queueing Networks

    Publication Year: 1987 , Page(s): 1107 - 1112
    Cited by:  Papers (2)
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    The use of queueing network models to analyze the performance of computer systems is widespread. Typically the analysis requires certain assumptions to be made. Even under such assumptions, the exact analysis of these models for the performance measures could be quite time consuming, especially when various alternate configurations of the system are to be evaluated. In some situations, bounds on the performance may often be adequate. This issue of obtaining reasonable bounds has hence been the subject of some discussion and a number of bounding techniques have been proposed over the past few years. In this paper we present a bounding technique for networks with a single class of customers that appears to be more effective than techniques previously reported. View full abstract»

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  • Constructing Test Cases for Partitioning Heuristics

    Publication Year: 1987 , Page(s): 1112 - 1114
    Cited by:  Papers (7)
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    In analyzing the effectiveness of min-cut partitioning heuristics, we are faced with the task of constructing ``random'' looking test networks with a prescribed cut-set size in its optimal partition. We present a technique for constructing networks over a given set of components that has been a priori partitioned into two parts. The networks have the property that the optimal partition, i.e., one that minimizes the size of the cut-set, is the predefined partition, and this partition has a cut-set of a given size. Furthermore, these networks can be designed to possess certain statistical properties, such as a desired mean and standard deviation for the number of components per net, so that they truly reflect the input space in the application domain. We also extend these techniques to the generalized partitioning problem. View full abstract»

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  • Self-Adjusting Networks for VLSI Simulation

    Publication Year: 1987 , Page(s): 1114 - 1120
    Cited by:  Papers (6)
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    Magnitude networks [1l, [2] have been used as a theoretical base for switch-level simulation of MOS VLSI circuits. We address in this paper the particular problem of evaluating the influence of switches in unknown state on the steady-state response of the network. A two-pass procedure based on local controllers attached to such switches is described and a hardware implementation is proposed which models magnitude networks as self-adjusting combinational circuits. View full abstract»

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  • A Note on Strongly Fault-Secure Sequential Circuits

    Publication Year: 1987 , Page(s): 1121 - 1123
    Cited by:  Papers (20)
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    It is proved that any sequential circuit with its next-state function d and output function w is strongly fault secure for unidirectional faults in d and w if i) the outputs of w are encoded in an unordered code, and ii) d and w are implemented with inverter-free circuits. View full abstract»

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  • MOS Test Pattern Generation Using Path Algebras

    Publication Year: 1987 , Page(s): 1123 - 1128
    Cited by:  Papers (11)
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    There is extensive evidence that the classical, stuck-at fault model, operating at the gate level, is inadequate for testing MOS VLSI circuits. By contrast, a ``nonclassical,'' switch-level model¿directly representing open and short circuits in the interconnect and transistors stuck-open or stuck-on¿allows important effects such as MOSFET bidirectionality and tristate behavior to be taken into account. This paper describes a new switch-level method for generating the singular cover of an MOS primitive gate using path algebras. The method yields tests to cover all specified interconnect open and short circuits, and all irredundant transistor stuck-open and stuck-on faults, should such tests exist. It relies on specification of an appropriate algebra by redefinition of the operators used in computing powers of a matrix. Two such algebras are required¿one to generate tests for open circuit faults and the other for short circuit faults. Test generation for networks of primitive gates is achieved in two stages: after deriving singular covers for the primitives, a variant of the D-algorithm with modified ``D-drive'' is used. The approach is unified and powerful, having the potential to detect parasitic latch behavior and to generate tests for any of the current MOS VLSI technologies. In common with most present automatic test generation methods, it is restricted to combinational logic. Practical limits on the size of circuit which can be dealt with appear comparable to those set by use of the classical D-algorithm. View full abstract»

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  • Performance Analysis of a Multiprocessor-Based Packet Switch in Networks with Link-Level Sliding-Window Flow Control

    Publication Year: 1987 , Page(s): 1128 - 1132
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    In the literature, performance studies on packet switches and link-level flow control procedures were treated separately. In this paper, we use a queueing network approach to analyze packet switch performance in terms of the combined effects of switch architectures and link-level flow-control procedures. Results of the study provide us with valuable insights about switch designs and unfold the relationship between switch performance and packet acknowledgment schemes. View full abstract»

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  • Binary Search Revisited: Another Advantage of Fibonacci Search

    Publication Year: 1987 , Page(s): 1132 - 1135
    Cited by:  Papers (2)  |  Patents (1)
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    Binary search method is a well-known and a fundamental technique to search a key out of an ordered table. Fibonacci serh is kind of binary search adopting nonequal splitting criterion for dividing the remaining part of the table. This paper clarifies another advantage of Fibonacci search, which has not been found so far. First, it is shown that, from the viewpoint of the amount of head movement, Fibonacci search gives more than 10 percent better efficiency than the ordinary binary search. Furthermore, we propose a novel variation of Fibonacci search, and show that it attains nearly 20 percent better efficiency in average than the ordinary binary search. View full abstract»

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  • Correction to ``The Fast Hartley Transform Algorithm''

    Publication Year: 1987 , Page(s): 1135 - 1136
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  • IEEE Computer Society Publications

    Publication Year: 1987 , Page(s): nil2
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    Freely Available from IEEE
  • [Front cover]

    Publication Year: 1987 , Page(s): c2
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    Freely Available from IEEE

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