IEEE Transactions on Computers

Issue 12 • Dec. 1987

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  • [Front cover]

    Publication Year: 1987, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1987, Page(s): nil1
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  • [Breaker page]

    Publication Year: 1987, Page(s): nil1
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  • Introduction to the Special Issue on Supercomputing

    Publication Year: 1987, Page(s):1393 - 1394
    Cited by:  Papers (1)
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  • Referee List

    Publication Year: 1987, Page(s): 1395
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  • Processor Allocation in an N-Cube Multiprocessor Using Gray Codes

    Publication Year: 1987, Page(s):1396 - 1407
    Cited by:  Papers (149)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2645 KB)

    The processor allocation problem in an n-dimensional hypercube (or an n-cube) multiprocessor is similar to the conventional memory allocation problem. The main objective in both problems is to maximize the utilization of available resources as well as minimize the inherent system fragmentation. A processor allocation strategy using the buddy system, called the buddy strategy, is discussed first an... View full abstract»

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  • Nearest-Neighbor Mapping of Finite Element Graphs onto Processor Meshes

    Publication Year: 1987, Page(s):1408 - 1424
    Cited by:  Papers (65)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3790 KB)

    The processor allocation problem is addressed in the context of the parallelization of a finite element modeling program on a processor mesh. A heuristic two-step, graph-based mapping scheme with polynomial-time complexity is developed: 1) initial generation of a graph partition for nearest-neighbor mapping of the finite element graph onto the processor graph, and, 2) a heuristic boundary refineme... View full abstract»

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  • Guided Self-Scheduling: A Practical Scheduling Scheme for Parallel Supercomputers

    Publication Year: 1987, Page(s):1425 - 1439
    Cited by:  Papers (252)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3814 KB)

    This paper proposes guided self-scheduling, a new approach for scheduling arbitrarily nested parallel program loops on shared memory multiprocessor systems. Utilizing loop parallelism is clearly most crucial in achieving high system and program performance. Because of its simplicity, guided self-scheduling is particularly suited for implementation on real parallel machines. This method achieves si... View full abstract»

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  • Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme

    Publication Year: 1987, Page(s):1440 - 1449
    Cited by:  Papers (42)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2540 KB)

    The degree to which high-speed vector processors approach their peak performance levels is closely tied to the amount of interference they encounter while accessing vectors in memory. In this paper we present an evaluation of a storage scheme that reduces the average memory access time in a vector-oriented architecture. A skewing scheme is used to map vector components into parallel memory modules... View full abstract»

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  • Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers

    Publication Year: 1987, Page(s):1450 - 1466
    Cited by:  Papers (107)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4211 KB)

    A new class of modular networks is proposed for hierarchically constructing massively parallel computer systems for distributed supercomputing and AI applications. These networks are called hypernets. They are constructed incrementally with identical cubelets, treelets, or buslets that are well suited for VLSI implementation. Hypernets integrate positive features of both hypercubes and tree-based ... View full abstract»

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  • Matrix Operations on a Multicomputer System with Switchable Main Memory Modules and Dynamic Control

    Publication Year: 1987, Page(s):1467 - 1484
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3984 KB)

    This paper presents an analysis and evaluation of the performance of a multicomputer system (SM3) in supporting two basic matrix operations, namely multiplication and inversion. The system supports the efficient execution of the above mentioned operations by 1) achieving a high-bandwidth data transfer among computers by switching main memory modules, 2) supporting network partitioning, 3) employin... View full abstract»

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  • Compiler Algorithms for Synchronization

    Publication Year: 1987, Page(s):1485 - 1495
    Cited by:  Papers (71)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2684 KB)

    Translating program loops into a parallel form is one of the most important transformations performed by concurrentizing compilers. This transformation often requires the insertion of synchronization instructions within the body of the concurrent loop. Several loop synchronization techniques are presented first. Compiler algorithms to generate synchronization instructions for singly-nested loops a... View full abstract»

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  • Checkpoint Repair for High-Performance Out-of-Order Execution Machines

    Publication Year: 1987, Page(s):1496 - 1514
    Cited by:  Papers (49)  |  Patents (111)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (10782 KB)

    Out-or-order execution and branch prediction are two mechanisms that can be used profitably in the design of supercomputers to increase performance. Proper exception handling and branch prediction miss handling in an out-of-order execution machine do require some kind of repair mechanism which can restore the machine to a known previous state. In this paper we present a class of repair mechanisms ... View full abstract»

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  • Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution

    Publication Year: 1987, Page(s):1515 - 1522
    Cited by:  Papers (27)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1679 KB)

    The issues of memory latency, synchronization, and distribution costs in multiprocessors are reviewed. The approaches taken by conventional and data flow architectures are contrasted in relation to these issues. It is pointed out that each approach fits well for a certain situation and that it is possible to have a common framework in which the two execution models can be mixed to suit the situati... View full abstract»

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  • The Warp Computer: Architecture, Implementation, and Performance

    Publication Year: 1987, Page(s):1523 - 1538
    Cited by:  Papers (166)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4588 KB)

    The Warp machine is a systolic array computer of linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A typical Warp array includes ten cells, thus having a peak computation rate of 100 MFLOPS. The Warp array can be extended to include more cells to accommodate applications capable of using the increa... View full abstract»

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  • 1987 Index IEEE Transactions on Computers Vol. C-36

    Publication Year: 1987, Page(s):1539 - 1550
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  • [Advertisement]

    Publication Year: 1987, Page(s): nil2
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  • Membership Application

    Publication Year: 1987, Page(s): 1551
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  • IEEE Computer Society Publications

    Publication Year: 1987
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  • [Front cover]

    Publication Year: 1987, Page(s): c2
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org