# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 23 of 23
• ### [Front cover]

Publication Year: 1987, Page(s): c1
| PDF (625 KB)
• ### IEEE Computer Society

Publication Year: 1987, Page(s): nil1
| PDF (190 KB)
• ### [Breaker page]

Publication Year: 1987, Page(s): nil1
| PDF (190 KB)
• ### VLSI Architectures for Multidimensional Fourier Transform Processing

Publication Year: 1987, Page(s):1265 - 1274
Cited by:  Papers (37)  |  Patents (3)
| | PDF (1812 KB)

It is often desirable in modern signal processing applications to perform two-dimensional or three-dimensional Fourier transforms. Until the advent of VLSI it was not possible to think about one chip implementation of such processes. In this paper several methods for implementing the multidimensional Fourier transform together with the VLSI computational model are reviewed and discussed. We show t... View full abstract»

• ### Coherent Cooperation Among Communicating Problem Solvers

Publication Year: 1987, Page(s):1275 - 1291
Cited by:  Papers (89)
| | PDF (4212 KB)

When two or more computing agents work on interacting tasks, their activities should be coordinated so that they cooperate coherently. Coherence is particularly problematic in domains where each agent has only a limited view of the overall task, where communication between agents is limited, and where there is no controller'' to coordinate the agents. Our approach to coherent cooperation in such... View full abstract»

• ### Applications Considerations in the System Design of Highly Concurrent Multiprocessors

Publication Year: 1987, Page(s):1292 - 1309
Cited by:  Papers (7)  |  Patents (2)
| | PDF (4102 KB)

A five-year series of studies, which ended in 1982 and which was supported in part by NASA and in part by Burroughs Corporation, led to the system design of a very large, very high-speed multiprocessor. This system was intended to solve large scientific problems, especially modeling problems such as those in computational aerodynamics. The performance objective was to sustain execution rates up to... View full abstract»

• ### On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic

Publication Year: 1987, Page(s):1310 - 1317
Cited by:  Papers (15)
| | PDF (1629 KB)

An on-line error-detectable high-speed multiplier is described. It is based on the multiplication algorithm which we have previously proposed. In the algorithm, the redundant binary representation each of whose digits is 0, 1, or -1 is used. The multiplier consists of an input encoder, a multiplication block, and an error checker. The input encoder encodes each primary input bit into the 1-out-of-... View full abstract»

• ### A Characterization of Ternary Simulation of Gate Networks

Publication Year: 1987, Page(s):1318 - 1327
Cited by:  Papers (10)
| | PDF (2453 KB)

Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we prove a somewhat modified version of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race... View full abstract»

• ### Optimal Checkpointing of Real-Time Tasks

Publication Year: 1987, Page(s):1328 - 1341
Cited by:  Papers (64)
| | PDF (2723 KB)

Analytical models for the design and evaluation of checkpointing of real-time tasks are developed. First, the execution of a real-time task is modeled under a common assumption of perfect coverage of on-line detection mechanisms (which is termed a basic model). Then, the model is generalized (to an extended model) to include more realistic cases, i.e., imperfect coverages of on-line detection mech... View full abstract»

• ### The Arithmetic Cube

Publication Year: 1987, Page(s):1342 - 1348
Cited by:  Papers (16)
| | PDF (1589 KB)

We present the design of a VLSI processor which can be programmed to compute the discrete Fourier transform of a sequence of n points and which achieves the theoretical AT2 lower bound of Ω(n2) for n ∈ n where n is an infinite set. Furthermore, since the set n is also sufficiently dense, the processor achieves for any n the theoretical AT2 lower bou... View full abstract»

• ### An Improved Algorithm for Constructing kth-Order Voronoi Diagrams

Publication Year: 1987, Page(s):1349 - 1354
Cited by:  Papers (26)
| | PDF (1892 KB)

The kth-order Voronoi diagram of a finite set of sites in the Euclidean plane E2 subdivides E2 into maximal regions such that all points within a given region have the same k nearest sites. Two versions of an algorithm are developed for constructing the kth-order Voronoi diagram of a set of n sites in O(n2 log n + k(n - k) log2 n) time, O(k(n - k)) stora... View full abstract»

• ### From Determinacy to Systaltic Arrays

Publication Year: 1987, Page(s):1355 - 1359
Cited by:  Papers (3)
| | PDF (1313 KB)

In this paper we extend a model of Karp and Miller for parallel computation. We show that the extended model is deterministic, in the sense that under different scheduling regimes each process in the computation consumes the same input and generates the same output. Moreover, if the computation halts, the final state is independent of scheduling. The model is applied to the generation of precedenc... View full abstract»

• ### Decoding of DBEC-TBED Reed-Solomon Codes

Publication Year: 1987, Page(s):1359 - 1363
Cited by:  Papers (9)  |  Patents (1)
| | PDF (835 KB)

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K bit DRAM's are organized in 32K ?? 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient lo... View full abstract»

• ### A Hardwired Generalized Algorithm for Generating the Logarithm Base-k by Iteration

Publication Year: 1987, Page(s):1363 - 1367
Cited by:  Papers (10)  |  Patents (2)
| | PDF (666 KB)

A number of previous works of computing the binary logarithm have been developed by a series of line approximations with moderate errors [1]-[3]. In this paper, a generalized iterative method for the logarithm of base-k evalution is proposed. We suggest that an integral constant k is used as a comparative index in each iteration. No table lookup is required. It can yield a more accurate and rapidl... View full abstract»

• ### Optimal Parallel Merging and Sorting Without Memory Conflicts

Publication Year: 1987, Page(s):1367 - 1369
Cited by:  Papers (55)  |  Patents (4)
| | PDF (648 KB)

A parallel algorithm is described for merging two sorted vectors of total length N. The algorithm runs on a shared-memory model of parallel computation that disallows more than one processor to simultaneously read from or write into the same memory location. It uses k processors where l ≤ k ≤ N and requires O(N/k + log k × log N) time. The proposed approach for merging leads t... View full abstract»

• ### A Generalization of Hybrid Fault Diagnosability

Publication Year: 1987, Page(s):1369 - 1374
Cited by:  Papers (4)
| | PDF (1354 KB)

A hybrid fault situation in a PMC system is a (bounded) combination of permanently and intermittently faulty units. Mallela and Masson [8] have given a general characterization of PMC systems for the diagnosis of hybrid fault situations. For this so-called th/thi diagnosability, when a syndrome takes on a form that is compatible with an allowable permanent fault situation, di... View full abstract»

• ### An Analytical Model for a Class of Processor-Memory Interconnection Networks

Publication Year: 1987, Page(s):1374 - 1378
Cited by:  Papers (1)
| | PDF (1018 KB)

The performance of aa delta interconnection network for multiprocessors is evaluated in a circuit switching environment An error is pointed out in previous literature and an exact analytical model is given for regeneration systems, where a connection request is considered lost if not immediately granted. An approximated numerical method is suggested for the correction of the analytical results, wh... View full abstract»

• ### Distributed Fault-Tolerance of Tree Structures

Publication Year: 1987, Page(s):1378 - 1382
Cited by:  Papers (15)
| | PDF (1175 KB)

Tree structures, as the interconnection structure in networks of many processing elements, have interesting features such as regularity ease of expansion, simple routing, simple addressing, suitability for VLSI/WSI implementation, etc. Distributed fault tolerance of these networks is considered. It is assumed that in these structures, there does not exist any central failure-free entity for provid... View full abstract»

• ### End-to-End Flow Control in Computer Networks with Noisy Channels and Quasi-Cut-Through Switching

Publication Year: 1987, Page(s):1382 - 1386
Cited by:  Papers (2)
| | PDF (877 KB)

Quasi-cut-through is a hybrid switching technique that has been recently proposed for computer networks. This paper deals with the end-to-end static flow control for computer networks using this hybrid switching technique. Two algorithms to handle the retransmissions of erroneous packets over noisy channels are analyzed and compared. Results are presented in terms of maximum user throughput, corre... View full abstract»

• ### Time Redundant Fault-Location in Bit-Sliced ALU's

Publication Year: 1987, Page(s):1387 - 1389
Cited by:  Papers (7)
| | PDF (591 KB)

A method of fault location in arithmetic and logic units (ALU's) is proposed. When the failures are confined to adjacent bit slices of the ALU's, the RESO (recomputing with shifted operands) based method can isolate the faulty bit slices by specifying a larger set of suspicious'' faulty bit slices, and, therefore, identify the definitely fault-free bit slices in ALU's. The method is applicable t... View full abstract»

• ### On Error Indication for Totally Self-Checking Systems

Publication Year: 1987, Page(s):1389 - 1392
Cited by:  Papers (14)  |  Patents (1)
| | PDF (748 KB)

Different ways of defining a totally self-checking system are discussed. Based on the discussion, a self-testing error indicator is defined and shown to provide a useful means to ensure concurrent error detection for fault-tolerant systems. A simple design for the self-testing error indicator is presented. View full abstract»

• ### IEEE Computer Society Publications

Publication Year: 1987, Page(s): nil2
| PDF (176 KB)
• ### [Front cover]

Publication Year: 1987, Page(s): c2
| PDF (203 KB)

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org