IEEE Transactions on Computers

Issue 1 • Jan. 1987

Filter Results

Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 1987, Page(s): c1
    Request permission for commercial reuse | |PDF file iconPDF (614 KB)
    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1987, Page(s): nil1
    Request permission for commercial reuse | |PDF file iconPDF (182 KB)
    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1987, Page(s): nil1
    Request permission for commercial reuse | |PDF file iconPDF (182 KB)
    Freely Available from IEEE
  • Editor's Notice

    Publication Year: 1987, Page(s): 1
    Request permission for commercial reuse | |PDF file iconPDF (1011 KB)
    Freely Available from IEEE
  • Clock Synchronization of a Large Multiprocessor System in the Presence of Malicious Faults

    Publication Year: 1987, Page(s):2 - 12
    Cited by:  Papers (47)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2570 KB)

    Clock synchronization in the presence of malicious faults is one of the main problems associated with the design of a multiprocessor system. Although over the past few years many different algorithms have been proposed for overcoming this problem, they are not suitable for a large real-time multiprocessor system due to their excessive time overhead, asymmetric structure, and/or large number of int... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a Hih-Speed Square Root Multiply and Divide Unit

    Publication Year: 1987, Page(s):13 - 23
    Cited by:  Papers (34)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2493 KB)

    In this paper radix-4 algorithms for square root and division are developed. The division algorithm evaluates the more useful function xz/y. These algorithms are shown to be suitable for implementing as a unified hardware unit which evaluates square root, division, and multiplication. Cost reductions in the hardware are obtained by use of gate arrays. A design based on the Motorola MCA2500 series ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

    Publication Year: 1987, Page(s):24 - 35
    Cited by:  Papers (580)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2873 KB)

    Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of programmer convenience. This is particularly true when the target machine is a programmable DSP chip. H... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Eliminating the Normalization Problem in Digit On-Line Arithmetic

    Publication Year: 1987, Page(s):36 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1746 KB)

    In digit on-line arithmetic, operands are introduced a digit at a time. After the first few operand digits have been introduced, the result begins to appear a digit at a time. This feature of digit on-line arithmetic allows a significant amount of overlapping of arithmetic operations. Digit on-line arithmetic can sometimes produce unnormalized results. This can present a problem for the divide and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault-Tolerant Decoders for Cyclic Error-Correcting Codes

    Publication Year: 1987, Page(s):47 - 63
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2948 KB)

    High-speed cyclic code decoders, which are central to modern communication systems, when implemented in dense very large scale integration (VLSI), are susceptible to pernicious momentary internal soft fails presenting a demanding error-control challenge. However, special structures inherent in such decoders offer new methods for incorporating distributed error control throughout their designs. The... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel Parsing on a One-Way Array of Finite-State Machines

    Publication Year: 1987, Page(s):64 - 75
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2400 KB)

    We show that a one-way two-dimensional iterative array of finite-state machines (2-DIA) can recognize and parse strings of any context-free language in linear time. What makes this result interesting and rather surprising is the fact that each processor of the array holds only a fixed amount of information (independent of the size of the input) and communicates with its neighbors in only one direc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Exact Performance Estimates for Multiprocessor Memory and Bus Interference

    Publication Year: 1987, Page(s):76 - 85
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2348 KB)

    Exact results are given for the processing power in a multibus multiprocessor with constant memory cycle times and geometric interrequest times. Both uniform and nonuniform memory accesses are considered. Such results have not previously been obtained. In order to derive these results we use a method of introducing time into Petri nets, called Generalized Timed Petri Nets (GTPN), that we have deve... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing

    Publication Year: 1987, Page(s):86 - 93
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1863 KB)

    This paper presents a new design for a ←self-checking checker for nonencoded multiinput combinational circuits. A built-in testing method is also stressed. The proposed checker, called a generalized prediction checker (GPC), has an extended and generalized form of conventional parity prediction checkers, and includes a duplication checker as a special case. A parity check matrix H imparts ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Unified View of Test Compression Methods

    Publication Year: 1987, Page(s):94 - 99
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1829 KB)

    A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of time compression schemes with respect to errors detected are developed. The use of two or more of these methods together is considered. Methods to design efficient test compression structures for built-in-tests are proposed. The feasibility of the proposed approach is dem... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dictionary Machines on Cube-Class Networks

    Publication Year: 1987, Page(s):100 - 105
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1367 KB)

    A dictionary is a data structure that supports insertion, deletion, and retrieval operations. To maintain a database, a dictionary machine accepts an arbitrary sequence of instructions at a constant rate. We designed two new VLSI dictionary machines on general-purpose networks that emulate the binary cube. One machine runs on a shuffle-exchange network. It includes a novel architecture to implemen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On Reducing Data Synchronization in Multiprocessed Loops

    Publication Year: 1987, Page(s):105 - 109
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1226 KB)

    In this correspondence we present and prove the correctness of an algorithm for reducing the number of synchronized memory references to shared data elements in multiprocessed loops. Optimizing compilers for shared memory multiprocessors can use this algorithm to reduce synchronization overhead. The algorithm has been implemented as a new module in the multiprocessors version of Parafrase, the res... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the Unavoidability of Metastable Behavior in Digital Systems

    Publication Year: 1987, Page(s):109 - 112
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (814 KB)

    Fault-free digital systems can fail as a result of metastable behavior when asynchronous inputs have critical timing combinations. The problem of metastable behavior is generally considered to be unavoidable in digital systems that synchronize asynchronous inputs. This correspondence extends previous results on the unavoidability of metastable behavior. The set of inputs to the digital system is g... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • (λT) Complexity Measures for VLSI Computations in Constant Chip Area

    Publication Year: 1987, Page(s):112 - 117
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1335 KB)

    The computational complexity measures introduced here are motivated by the trend to higher VLSI integration levels (rather than increased chip area) to accomplish solutions to larger problem instances. It seems that the increase in the computational power of VLSI circuits can be mainly attributed to the reduction in the minimum feature size rather than to an increase in the chip area. In view of t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Systolic Arrays for Matrix Transpose and Other Reorderings

    Publication Year: 1987, Page(s):117 - 122
    Cited by:  Papers (17)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (785 KB)

    In this correspondence, a systolic array is described for computing the transpose of an n × n matrix in time 3n - 1 using n2 switching processors and n2 bit buffers. A one-dimensional implementation is also described. Arrays are also given to take a matrix in by rows and put it out by diagonals, and vice versa. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Exact Product Form Solution for Queueing Networks with Blocking

    Publication Year: 1987, Page(s):122 - 125
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (838 KB)

    This work investigates closed queueing networks with blocking composed of two stations with multiple servers. Blocking occurs when a job wanting to enter a full station is forced to remain in its source station, thus blocking the source station until room is available at the destination station. This type of blocking is known as classical blocking. We show that, for a two-station closed queueing n... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Call for papers

    Publication Year: 1987, Page(s): 126
    Request permission for commercial reuse | |PDF file iconPDF (91 KB)
    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1987, Page(s):127 - 128
    Request permission for commercial reuse | |PDF file iconPDF (257 KB)
    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1987, Page(s): nil2
    Request permission for commercial reuse | |PDF file iconPDF (184 KB)
    Freely Available from IEEE
  • Information for Authors

    Publication Year: 1987, Page(s): c2
    Request permission for commercial reuse | |PDF file iconPDF (201 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org