# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 22 of 22
• ### [Front cover]

Publication Year: 1985, Page(s): c1
| PDF (548 KB)
• ### IEEE Computer Society

Publication Year: 1985, Page(s): nil1
| PDF (182 KB)
• ### [Breaker page]

Publication Year: 1985, Page(s): nil1
| PDF (182 KB)
• ### The Exclusive-Writer Approach to Updating Replicated Files in Distributed Processing Systems

Publication Year: 1985, Page(s):489 - 500
Cited by:  Papers (9)  |  Patents (10)
| | PDF (3179 KB)

Consistency control protocols can be classified as either pessimistic or optimistic. Pessimistic protocols check for conflicting file accesses before a transaction references shared files; this prevents transaction restarts but adds intercomputer synchronization delays to execution response times TE. Optimistic protocols avoid intercomputer synchronization delays for TE, but ... View full abstract»

• ### The Structure of Periodic Storage Schemes for Parallel Memories

Publication Year: 1985, Page(s):501 - 505
Cited by:  Papers (29)  |  Patents (2)
| | PDF (1995 KB)

The use of parallel memories in SIMD machines requires special data mappings, known as skewing schemes,'' for storing matrices for the purposes of efficient vector computations. Some schemes have explicitly been implemented in current super-computers. Periodic skewing schemes are of particular interest because they have a regular structure and can be represented by simple formulas. In this paper... View full abstract»

• ### A Versatile Mechanism to Move Data in an Array Processor

Publication Year: 1985, Page(s):506 - 522
Cited by:  Papers (7)  |  Patents (2)
| | PDF (3239 KB)

Selection of elements and alignment of operands are fundamental operations on data, just as are arithmetic operations. Whereas sophisticated algorithms have been devised for the latter, vector processors usually lack a flexible and efficient routing unit. This is especially true of SIMD computers, to which the present study is devoted. Examples of required manipulations are: transfer, shift, diffu... View full abstract»

• ### Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables

Publication Year: 1985, Page(s):523 - 541
Cited by:  Papers (7)
| | PDF (3900 KB)

This paper first discusses the symmetric property of the minimal covering problem in terms of group theory and then the use of this property in the branch-and-bound method for solving the problem. Computational results on solving sample problems are shown to demonstrate the improvement of computational efficiency of the branch-and-bound method by the utilization of the symmetric property. The samp... View full abstract»

• ### On Permuting Properties of Regular Rectangular SW-Banyans

Publication Year: 1985, Page(s):542 - 546
Cited by:  Papers (10)
| | PDF (963 KB)

This correspondence analyzes the permuting properties of a reconfigurable multicomputer architecture based on a regular rectangular SW-banyan interconnection network with arbitrary fan-out and an arbitrary number of stages. An analytical expression for the total number of distinct permutations performable by a rectangular SW-banyan (in one pass) is derived. It is shown how the combinatorial power ... View full abstract»

• ### Complete Binary Spanning Trees of the Eight Nearest Neighbor Array

Publication Year: 1985, Page(s):547 - 549
Cited by:  Papers (3)
| | PDF (641 KB)

Complete binary spanning trees of an n x n array of processors with an eight nearest neighbor interconnection pattern exist for a limited value of n. These spanning trees provide a fast route to accumulate information from all processors of the array, and allow certain problems to be solved as efficiently on an eight-neighbor array as on a tree-structured array. The condition under which complete ... View full abstract»

• ### Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays

Publication Year: 1985, Page(s):549 - 553
Cited by:  Papers (9)
| | PDF (924 KB)

The increasing number of applications of programmable logic arrays (PLA's) has evoked the development of test generation methods for these circuits. There are known methods for complete single contact fault detection test set generation. These test sets fail to detect all multiple faults in a PLA due to the phenomenon of masking. In this correspondence, we present a method to quantitively predict ... View full abstract»

• ### Detecting I/O and Internal Feedback Bridging Faults

Publication Year: 1985, Page(s):553 - 557
Cited by:  Papers (16)
| | PDF (1024 KB)

The testing of bridging faults (short circuits) has become increasingly important with the increasing density in VLSI (very large scale integration) chips. Yet very little work has been done in this area. In this correspondence, based on a two-state sequential machine model, we present the conditions for a circuit with feedback bridgings to oscillate and to exhibit stable sequential behavior. It i... View full abstract»

• ### SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems

Publication Year: 1985, Page(s):557 - 562
Cited by:  Papers (17)  |  Patents (5)
| | PDF (1236 KB)

SEC-ED-DED codes are single error correcting and double error detecting while simultaneously providing byte error detection. SEC-BED-DED codes are constructed for byte lengths of 5 and larger. For many byte lengths and code lengths, these codes require fewer check bits or have implementation advantages when compared to other SEC-BED-DED codes. View full abstract»

• ### Counting Sequences with Large Local Distance

Publication Year: 1985, Page(s): 562
| | PDF (225 KB)

The 2n n-bit vectors can be ordered so that any vector in the sequence has some minimum Hamming distance from any vector near it in the sequence. View full abstract»

• ### A Maximally Parallel Balancing Algorithm for Obtaining Complete Balanced Binary Trees

Publication Year: 1985, Page(s):563 - 565
Cited by:  Papers (9)
| | PDF (589 KB)

We present a new iterative balancing algorithm for binary trees of size N = 2n -1 by exploiting the similarity of pointer restructuring at each level. We also extract parallelism from this algorithm to yield a constant time complexity balancing algorithm for an N-processor configuration. This achieves the theoretical limit of speedup possible. View full abstract»

• ### Insertion Networks

Publication Year: 1985, Page(s):565 - 570
| | PDF (802 KB)

The problem of inserting an item in a list is frequently encountered in various application fields such as sorting, compiling, etc. It is shown that the insertion of an item in a list of N members may be realized at a cost proportional to N and within a delay proportional to log N. View full abstract»

• ### Some Aspects of the Dynamic Behavior of Hierarchical Memories

Publication Year: 1985, Page(s):570 - 573
Cited by:  Papers (1)
| | PDF (828 KB)

In a computer system with a cache memory, the cache is effectively empty following a job switch, leading to a low hit rate and consequently lowered performance until the cache becomes reasonably full. The analysis shows that a job must run for several milliseconds before the average performance approaches that expected from a steady-state analysis. Care may therefore be needed in designing memory ... View full abstract»

• ### A Radix-4 FFT Using Complex RNS Arithmetic

Publication Year: 1985, Page(s):573 - 576
Cited by:  Papers (32)
| | PDF (562 KB)

Recent advancements in residue arithmetic have given rise to a complex number system variant which better than halves RNS multiplication complexity. This advantage is applied to the problem of implementing a high-speed radix-4 RNS FFT. It is shown that a significant improvement in both complexity and speed can be achieved. View full abstract»

• ### Polynomial Division on Systolic Arrays

Publication Year: 1985, Page(s):577 - 578
Cited by:  Papers (8)
| | PDF (361 KB)

In this correspondence we show how long division of polynomials can be performed in a pipelined fashion on a linear systolic array in linear time. View full abstract»

• ### A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays

Publication Year: 1985, Page(s):578 - 584
Cited by:  Papers (14)
| | PDF (1325 KB)

We study here a formal version of a strategy for constructing fault-tolerant VLSI processor arrays in an environment of wafer-scale integration. The strategy achieves tolerance to faults by running buses past the implemented PE's and interconnecting the fault-free ones into an array of the desired structure by having PE's tap into the bank of buses. Earlier studies [12] have shown this strategy to... View full abstract»

• ### Correction to "Computational Geometry - A Survey"

Publication Year: 1985, Page(s): 584
Cited by:  Papers (5)
| | PDF (155 KB)

First Page of the Article
View full abstract»

• ### IEEE Computer Society Publications

Publication Year: 1985, Page(s): nil2
| PDF (178 KB)
• ### [Front cover]

Publication Year: 1985, Page(s): c2
| PDF (200 KB)

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org