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Computers, IEEE Transactions on

Issue 8 • Date Aug. 1984

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 1984 , Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1984 , Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1984 , Page(s): nil1
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  • Precise Scientific Computation with a Microprocessor

    Publication Year: 1984 , Page(s): 685 - 690
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1421 KB)  

    When a high-level programming language is used for scientific computation, usually one must use standard floating point and choose the precision¿single, double, or higher¿before one's program executes. This paper describes a modified Basic that accommodates the advanced computation techniques of dynamic adjustable precision and interval arithmetic. This language¿Precision Basic or Pbasic¿allows a user to routinely obtain his n decimal place answers accurate to the last decimal place. An interpreter for this modified Basic was recently completed that runs on a Z-80 microprocessor. Some features of the interpreter are described. View full abstract»

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  • Estimation of Intermodule Communication (IMC) and Its Applications in Distributed Processing Systems

    Publication Year: 1984 , Page(s): 691 - 699
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1988 KB)  

    Communication among program modules plays an important role in the performance of distributed processing systems. In this paper, a model for estimating intermodule communication (IMC) is developed. The model derives communication volume based on module invocation rates and file access probabilities via the control-and-data-flow graph. The IMC model is validated by simulation experiments. Interprocessor communication (IPC) and system resources utilization can be estimated from the IMC. We show that IMC and IPC are useful in finding good module assignments in distributed processing systems. View full abstract»

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  • A Comparative Study of Distributed Resource Sharing on Multiprocessors

    Publication Year: 1984 , Page(s): 700 - 711
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2346 KB)  

    In this paper we have studied the interconnection of resources to multiprocessors and the distributed scheduling of these resources. For a given interconnection network, the resource-mapping problem entails the search of one of the free resources which can be connected to each requesting processor. To prevent the bottleneck of sequential scheduling, a request without any destination address is given to the network, and the network is responsible for finding the necessary resource and connecting it to the processor. The addressing mechanism is thus distributed in the network. Three different classes of networks have been investigated: namely, single shared bus, multiple shared buses, and multistage dynamic networks. In each case, the scheduling algorithm is described, and the tradeoffs of different network configurations are studied. The resource-sharing networks are a generalization of conventional interconnection networks with routing tags in which all the resources are of different types. View full abstract»

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  • An Instruction Fetch Unit for a High-Performance Personal Computer

    Publication Year: 1984 , Page(s): 712 - 730
    Cited by:  Papers (1)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4243 KB)  

    The instruction fetch unit (IFU) of the Dorado personal computer speeds up the emulation of instructions by prefetching, decoding, and preparing later instructions in parallel with the execution of earlier ones. It dispatches the machine's microcoded processor to the proper starting address for each instruction, and passes the instruction's fields to the processor on demand. A writeable decoding memory allows the IFU to be specialized to a particular instruction set, as long as the instructions are an integral number of bytes long. There are implementations of specialized instruction sets for the Mesa, Lisp, and Smalltalk languages. The IFU is implemented with a six-stage pipeline, and can decode an instruction every 60 ns. Under favorable conditions the Dorado can execute instructions at this peak rate (16 mips). View full abstract»

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  • Systolic VLSI Arrays for Polynomial GCD Computation

    Publication Year: 1984 , Page(s): 731 - 736
    Cited by:  Papers (46)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1578 KB)  

    The problem of finding a greatest common divisor (GCD) of any two nonzero polynomials is fundamental to algebraic and symbolic computations, as well as to the decoder implementation for a variety of error-correcting codes. This paper describes new systolic arrays that can lead to efricient VLSI solutions to both the GCD problem and the extended GCD problem. View full abstract»

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  • A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications

    Publication Year: 1984 , Page(s): 737 - 739
    Cited by:  Papers (19)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB)  

    Error correcting codes are widely used in memory systems to increase reliability. Especially in a memory systern that uses byte-organized memory chips, which each contain b (≫1) output bits, a single chip failure is likely to affect many bits within a byte. Single-bit error correcting-double bit error detecting-single b-bit byte error detecting codes (SEC-DED-SbED codes) are suitable for increasing the reliability of memory system. This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4. The code length is 2r-1 - 2[r/2], where r is the number of check bits and [ ] denotes the ceiling or next largest integer. The proposed SEC-DED-S4ED codes are the best-known codes. View full abstract»

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  • On Generating the N-ary Reflected Gray Codes

    Publication Year: 1984 , Page(s): 739 - 741
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    The definition of the N-ary reflected Gray code is given. Two recursive algorithms for generating the N-ary reflected Gray codes are presented: one algorithm is coded directly from the definition; another algorithm is derived from the sequencing orders of digits in the N-ary reflected Gray codes. It is shown that these two algorithms are equivalent functionally. Furthermore, it is proven that the N-ary reflected Gray code is cyclic when its radix is even, but not cyclic, in general, when its radix is odd. View full abstract»

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  • On Separable Unordered Codes

    Publication Year: 1984 , Page(s): 741 - 743
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    Unordered codes have proven useful for designing failsafe, fault-secure, and self-checking logic circuits. In many applications it may be desirable to have separate information bits and check bits, i.e., a separable code. This correspondence gives a procedure for adding check bits to a set of information k-tuples to produce an unordered code. The general case where not all 2k possible k-tuples are used is considered. For an arbitrary set of k-tuples, the minimum number of check bits is shown. View full abstract»

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  • A Testable PLA Design with Low Overhead and High Fault Coverage

    Publication Year: 1984 , Page(s): 743 - 745
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB)  

    A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test. View full abstract»

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  • A New PLA Design for Universal Testability

    Publication Year: 1984 , Page(s): 745 - 750
    Cited by:  Papers (37)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1183 KB)  

    A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA. The proposed design has the following properties. 1) It can be tested with function-independent test patterns; hence, no test pattern generation is required. 2) The amount of extra hardware is significantly decreased compared to the previous designs of universally testable PLA's. 3) Very high fault coverage is achieved, i. e., all single and multiple stuck faults, crosspoint faults, and adjacent line bridging faults are detected. 4) It is appropriate for built-in testing approaches. 5) It can be applied to the high-density PLA's using array folding techniques. View full abstract»

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  • On the Complexity of Estimating the Size of a Test Set

    Publication Year: 1984 , Page(s): 750 - 753
    Cited by:  Papers (35)
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    Most NP-completeness results for test generation problems involve a reduction to the redundancy problem, which explicitly encodes the satisfiability problem. In this correspondence we investigate the complexity of a more modest problem¿that of estimating the size of a test set under the constraint that the circuit is irredundant. We show that even this constrained problem is NP-hard in the strong sense. View full abstract»

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  • Self-Testing Embedded Parity Checkers

    Publication Year: 1984 , Page(s): 753 - 756
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (698 KB)  

    It is shown that if a 4-by-n binary matrix has four distinct even-parity rows such that each column has exactly two 0's and two 1's, then there exists a totally self-checking even-parity checker that is tested by the four rows of this matrix. The utility of this result in designing self-testing embedded parity checkers is described. View full abstract»

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  • A Diagnosis Algorithm for the BGM System Level Fault Model

    Publication Year: 1984 , Page(s): 756 - 758
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB)  

    A ¿diagnosable system is a system in which all faults may be identified from the test results, provided that the number of faults does not exceed ¿. In this correspondence we present an algorithm that may be used for the diagnosis of the system level BGM fault model proposed by Barsi, Grandoni, and Maestrini, whenever the system is ¿-diagnosable and the number of faults is at most ¿. View full abstract»

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  • Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults

    Publication Year: 1984 , Page(s): 758 - 761
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    Undetectable bridging faults between two arbitrary leads, which may produce feedback loops, in a unate two-level irredundant AND-OR network are anlyzed and their effect on stuck-at fault detection tests is explored. As a result, any complete test set for single stuck-at faults proves to still remain valid in the presence of undetectable bridging faults. View full abstract»

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  • Signature Testing of Sequential Machines

    Publication Year: 1984 , Page(s): 762 - 764
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (654 KB)  

    A new approach to the testing of sequential machines is presented which employs signature analysis. In the conventional scheme of testing sequential finite state machines, distinguishing and transfer sequences are used. For the purposes of testing sequential machines by signature analysis, a signature distinguishing sequence is defined. An algorithm for augmenting a sequential machine by introducing an extra input is presented. This yields a sequential machine that has a signature distinguishing sequence. The additional cost in terms of the chip area for a programmable logic array (PLA) implementation is calculated. View full abstract»

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  • Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks

    Publication Year: 1984 , Page(s): 765 - 769
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1019 KB)  

    A method is described for the derivation of fault signatures for the detection of stuck-at faults in single-output combinational networks. These signatures consist of a set of values derived from the network. Any single stuck-at fault causes at least one value to change. The fault signatures developed are a generalization of syndrome testing. The technique is developed in the Rademacher-Walsh spectral domain but is easily implemented using conters and basic gates. View full abstract»

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  • A Classification of Cube-Connected Networks with a Simple Control Scheme

    Publication Year: 1984 , Page(s): 769 - 772
    Cited by:  Papers (1)
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    The correspondence presents three classes of cube-connected networks with individual stage control based on a group theoretic modeling of interconnection networks. It is shown that these classes of networks retain nonisomorphic groups of permutations. Although the permutations realizable by such networks are rather limited in number, the simplicity of their control scheme makes them attractive. Moreover, the interconnection power of these networks can be enhanced by simulating the networks which belong to one class by any member of that class. View full abstract»

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  • Correction to ``Performance Evaluation of the Computer Network Dynamic Congestion Table Algorithm''

    Publication Year: 1984 , Page(s): 772
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  • IEEE Computer Society Publications

    Publication Year: 1984 , Page(s): nil2
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    Freely Available from IEEE
  • [Front cover]

    Publication Year: 1984 , Page(s): c2
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    Freely Available from IEEE

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
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e-mail: pmo@computer.org