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IEEE Transactions on Computers

Issue 7 • July 1984

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 1984, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1984, Page(s): nil1
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  • [Breaker page]

    Publication Year: 1984, Page(s): nil1
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  • Editor's Notice

    Publication Year: 1984, Page(s): 589
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  • List of referees

    Publication Year: 1984, Page(s):590 - 591
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  • Modeling the Weather with a Data Flow Supercomputer

    Publication Year: 1984, Page(s):592 - 603
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2782 KB)

    Data flow computers promise efficient parallel computation limited in speed only by data dependencies in the calculation being performed. At the Massachusetts Institute of Technology Laboratory for Computer Science, the Computation Structures Group is working to design practical data flow computers that can outperform conventional supercomputers. Since data flow computers differ radically in struc... View full abstract»

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  • Database Applications of the FETCH-AND-ADD Instruction

    Publication Year: 1984, Page(s):604 - 612
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3011 KB)

    The FETCH-AND-ADD instruction provides for synchronization of multiple processes in a parallel manner. This paper explores the use of FETCH-AND-ADD in the context of database systems. We show how to enqueue locks, detect lock conflicts, and release locks without resorting to critical program sections that require mutual exclusion during execution. The scheme is compatible with a variant of lock ma... View full abstract»

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  • Fast Burst Error-Correction Scheme with Fire Code

    Publication Year: 1984, Page(s):613 - 618
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1532 KB)

    A fast burst error-correction decoder is proposed. It can be used for high-speed decoding of a burst error-correcting Fire code having the generator polynomial G(x) = (1 + xC)p(x), where p(x) is irreducible and of degree m and the degree of G (x) is r = c + m, r being the number of redundancy bits. The decoder needs at most r -1 cycles to find both the error burst pattern and its locati... View full abstract»

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  • Shuffling with the Illiac and PM2I SIMD Networks

    Publication Year: 1984, Page(s):619 - 625
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1929 KB)

    Two SIMD single-stage interconnection networks which have been proposed and studied in the literature are the Illiac type and PM2I. The ability of the Illiac and PM2I networks to perform the shuffle data permutation in an SIMD machine with N processors is examined. Two algorithms for an SIMD or multiple-SIMD machine with the PM2I network to perform the shuffle are given. One algorithm is used in t... View full abstract»

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  • Hardware Task/Processor Scheduling in a Polyprocessor Environment

    Publication Year: 1984, Page(s):626 - 636
    Cited by:  Papers (10)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2361 KB)

    A special bus structure, the SYNCBUS, is proposed, which supports task scheduling by hardware. It can be used efficiently in multiprocessor-(all processors identical) and polyprocessor-systems (different pools of processors) running real-time multitasking software with a dynamic load distribution. Tasks waiting for execution create prioritized interrupts, which are distributed over all available p... View full abstract»

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  • Scheduling Multipipeline and Multiprocessor Computers

    Publication Year: 1984, Page(s):637 - 645
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2106 KB)

    We develop good heuristics to schedule tasks on computers that have multiple pipelines or multiple asynchronous processors. We also consider the case when different pipes or processors run at different speeds. View full abstract»

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  • An Architecture for Bitonic Sorting with Optimal VLSI Performnance

    Publication Year: 1984, Page(s):646 - 651
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1655 KB)

    We propose a class of designs of a new interconnection network, the pleated cube-connected cycles (PCCC), which can impleement stable bitonic sorting of n records of size q in area A = O(q2n2/T2), where T, the computation time, is in the range [Ω(q log2 n), O(q √n/(q+ log n))]. Thus, this network is an AT2,/R-optimal bitonic so... View full abstract»

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  • Serial/Parallel Convolvers

    Publication Year: 1984, Page(s):652 - 667
    Cited by:  Papers (42)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2622 KB)

    A new type of convolver is presented. This type utilizes a kind of systolic array where the basic cell is mainly a full adder and the basic structure is a serial/parallel multiplier. A new formalism is developed which encompasses the whole family of serial/parallel multipliers. All these designs can be carried over to the design of convolvers since the convolution formula has the same structure on... View full abstract»

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  • VLSI Sorting with Reduced Hardware

    Publication Year: 1984, Page(s):668 - 671
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (957 KB)

    We propose a new VLSI architecture which allows many problems to be solved quite efficiently on chips with very small processing areas. We consider in detail the sorting problem and show how it can be solved quickly and elegantly on our model. We show that sorting n numbers can be done on a chip with processing area A = o(n) with an almost optimal speedup in a network with mesh-connected interconn... View full abstract»

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  • Finding Rectangle Intersections by Divide-and-Conquer

    Publication Year: 1984, Page(s):671 - 675
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1126 KB)

    In this correspondence we reconsider three geometrical problems for which we develop divide-and-conquer algorithms. The first problem is to find all pairwise intersections among a set of horizontal and vertical line segments. The second is to report all points enclosures occurring in a mixed set of points and rectangles, and the third is to find all pairwise intersections in a set of isooriented r... View full abstract»

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  • Adjacencies Between the Cycles of a Shift Register with Characteristic Polynomial (1 + x)n

    Publication Year: 1984, Page(s):675 - 677
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (638 KB)

    It is shown that the set of cycles of a linear feedback shift register with characteristic polynomial (1 + x)n are at most doubly adjacent. View full abstract»

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  • Cascading Transmission Gates to Enhance Multiplier Performance

    Publication Year: 1984, Page(s):677 - 679
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (650 KB)

    A high-speed Wallace-tree type combinational multiplier chip has been fabricated as a technology demonstration device using 1.5 μm NMOS processing. Multiply rates well in excess of 40 mHz have been obtained from laboratory devices. Extensive use of cascaded MOS transmission-gate (or steering) logic resulted in worthwhile improvements in power, average gate delay, and device topology. View full abstract»

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  • Multivalued Logic and Fuzzy Logic--Their Relationship, Minimization, and Application to Fault Diagnosis

    Publication Year: 1984, Page(s):679 - 681
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (654 KB)

    The k-valued Kleene functions over Kleene algebra (instead of over Post algebra) are defined. Multivalued logic and fuzzy logic are studied in the light of lattice theory. It is shown that all Kleene k-valued logic (k = 3 or more) have the same algebraic structure as fuzzy logic through lattice isomorphism. As a by-product, an asymptotic formula and upper bound for enumeratinlg fuzzy switching fun... View full abstract»

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  • Comments on "The Reliability of Periodically Repaired n - 1/n Parallel Redundant Systems

    Publication Year: 1984, Page(s): 681
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (211 KB)

    In the correspondence1 the author presented an approximate formula for the average failure rate in a periodically repaired n - 1/n parallel redundant system. It was assumed that the system consists of n parallel identical elements, each of which has a constant failure rate ??. The system is also repaired every T hours. It was shown that an approximate expression for the average failure ... View full abstract»

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  • Correction to ``Finite Precision Rational Arithmetic: An Arithmetic Unit''

    Publication Year: 1984, Page(s): 682
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  • IEEE copyright form

    Publication Year: 1984, Page(s):683 - 684
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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): nil2
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  • [Front cover]

    Publication Year: 1984, Page(s): c2
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org