IEEE Transactions on Computers

Issue 1 • Jan. 1984

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  • [Front cover]

    Publication Year: 1984, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1984, Page(s): nil1
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  • [Breaker page]

    Publication Year: 1984, Page(s): nil1
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  • Editor's Notice

    Publication Year: 1984, Page(s): 1
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  • On the 2-Dimensional Channel Assignment Problem

    Publication Year: 1984, Page(s):2 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (903 KB)

    We consider the 2-dimensional channel assignment problem: given a set S of iso-oriented rectangles (whose sides are parallel to the coordinate axes), find a minimum number of planes (channels) to which only nonoverlapping rectangles are assigned. This problem is equivalent to the coloring problem of the rectangle intersection graph G = (V, E), in which each vertex in V corresponds to a rectangle a... View full abstract»

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  • Bit-Sequential Arithmetic for Parallel Processors

    Publication Year: 1984, Page(s):7 - 20
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2710 KB)

    A bit-sequential processing element with O(n) complexity is described, where n is the wordlength of the operands. The operations performed by the element are A * B + C * D, A/B, and √A. The operands are fixed point or floating point numbers with variable precision. The concept of semi-on-line algorithms is introduced. A processing element that uses semi-on-line algorithms produces a result... View full abstract»

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  • On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

    Publication Year: 1984, Page(s):21 - 27
    Cited by:  Papers (79)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1728 KB)

    Fault-tolerance is undoubtedly a desirable property of any processor array. However, increased design and implementation costs should be expected when fault-tolerance is being introduced into the architecture of a processor array. When the processor array is implemented within a single VLSI chip, these cost increases are directly related to the chip silicon area. Thus, the increase in area should ... View full abstract»

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  • Memory Allocations for Multiprocessor Systems That Incorporate Content-Addressable Memories

    Publication Year: 1984, Page(s):28 - 44
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4136 KB)

    For associative processing and relational data bases characterized by sequential memory search, it is convenient to store a sequence of data files in a content-addressable memory since it can perform two concurrent data base operations at a time (search and update, search and delete, etc.) and the sequential nature of its operation is in conformity with the sequential nature of maintenance and upd... View full abstract»

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  • Parallelism and Array Processing

    Publication Year: 1984, Page(s):45 - 78
    Cited by:  Papers (38)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7695 KB)

    Modern computing, as well as the historical development of computing, has been dominated by sequential monoprocessing. Yet there is the alternative of parallelism, where several processes may be in concurrent execution. This alternative is discussed, in which the main developments involving parallelism are considered both from the standpoint of computing systems and that of applications than can e... View full abstract»

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  • Random Pattern Testability

    Publication Year: 1984, Page(s):79 - 90
    Cited by:  Papers (98)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2555 KB)

    A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage t... View full abstract»

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  • A Local Selection Algorithm for Switching Function Minimization

    Publication Year: 1984, Page(s):91 - 97
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1513 KB)

    The minimization algorithms which do not require any preliminary generation of all the prime implicants (PI's) of a function are the most efficient. In this work a new algorithm is described which follows such an approach. It is based on a local selection of PI's carried out by examining a set of vertices whose number is never greater than the number of PI's of a minimum cost cover. This algorithm... View full abstract»

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  • Graph Functions of Boolean Functions

    Publication Year: 1984, Page(s):97 - 99
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (510 KB)

    We introduce and characterize those Boolean functions (graph functions) which can be regarded as characteristic functions of graphs of other Boolean functions. An algorithm for detecting these functions is also presented. Finally, we discuss the complexity of computing a Boolean function which can be regarded as a graph function. View full abstract»

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  • A Systolic Design for Connectivity Problems

    Publication Year: 1984, Page(s):99 - 104
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1149 KB)

    In this paper we present a design, suited to VLSI implementation, for a one-dimensional array to solve graph connectivity problems. The computational model is relatively primitive in that only the two end cells of the array can interact with the external environment and only adjacent cells in the array are allowed to communicate. However, we show that an array of n + 1 cells can be used for a grap... View full abstract»

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  • Embedding Tree Structures in VLSI Hexagonal Arrays

    Publication Year: 1984, Page(s):104 - 107
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB)

    Tree structures have been proposed for special-purpose and general-purpose multiprocessors due to their desirable property of logarithmic path from the root to any leaf element. Since only local communication among processors is needed in tree structures, they are well suited for the VLSI technology. Such an implementation requires an area-economical mapping of a tree on a plane. Novel mapping sch... View full abstract»

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  • [Advertisement]

    Publication Year: 1984, Page(s): 108
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  • IEEE copyright form

    Publication Year: 1984, Page(s): 109
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  • [Advertisement]

    Publication Year: 1984, Page(s): 110
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  • IEEE copyright form

    Publication Year: 1984, Page(s):111 - 112
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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): nil2
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  • [Front cover]

    Publication Year: 1984, Page(s): c2
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org