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Computers, IEEE Transactions on

Issue 6 • Date June 1973

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Displaying Results 1 - 22 of 22
  • [Front cover]

    Page(s): c1
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  • IEEE Computer Society

    Page(s): nil1
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  • [Breaker page]

    Page(s): nil1
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  • Computation Times of Arithmetic and Boolean Functions in (d, r) Circuits

    Page(s): 552 - 555
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    A (d, r) circuit is a d-valued logical circuit in which each element has fan-in at most r and can compute any r-argument d-valued logical function in unit time. In this paper we review results previously published on the computation time of such circuits for addition and multiplication and for computation of general Boolean functions. We also explicitly state hitherto unpublished but known results on the time necessary to divide in such circuits. View full abstract»

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  • The Status of Investigations into Computer Hardware Design Based on the Use of Continued Fractions

    Page(s): 555 - 560
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    The purpose of this paper is to demonstrate that representations of numbers other than positional notation may lead to practical hardware realizations for digital calculation of classes of algorithms. This paper describes current research in the use of continued fractions. Although practicality has not been demonstrated, theoretical results are promising. View full abstract»

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  • Radix-16 Evaluation of Certain Elementary Functions

    Page(s): 561 - 566
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    This paper describes a family of algorithms for evaluation of a class of elementary functions including division, logarithms, and exponentials. The main objective is to demonstrate the feasibility of higher radix implementations, in particular, radix 16, and to compare performance with radix 2. The emphasis is not on optimality of a single algorithm, but rather on the optimality of a class of algorithms. An attempt to implement a much wider class of functions than is presently done in arithmetic units is encouraged by the current level of digital technology and the existence of suitable algorithms. Besides the definitions of the algorithms, which are based on continued products and continued sums, details related to implementation are discussed. View full abstract»

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  • Arithmetic Algorithms for Error-Coded Operands

    Page(s): 567 - 572
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    A set of arithmetic algorithms is described for operands that are encoded in the ``AN'' error-detecting code with the low-cost check modulus A = 2a - 1. The set includes addition additive inverse (complementation), multiplication, division, roundoff, and two auxiliary algorithms: ``multiply by 2a - 1,'' and ``divide by 2a - 1.'' The design of a serial radix-16 processor is presented in which these algorithms are implemented for the low-cost AN code with A = 15. This processor has been constructed for the Jet Propulsion Laboratory STAR computer. The adaptation of ``two's complement'' arithmetic for an inverse-residue code is also described. View full abstract»

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  • Analyzed Binary Computing

    Page(s): 573 - 576
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    A single format for the representation of numbers in a computer is proposed to accommodate both exact and inexact quantities. A consistent set of rules is described for addition (subtraction), multiplication, and division of such quantities, both within their separate types, as well as in combination. Error correlation aside, the propagation of inherent errors is monitored in operations with at least one imprecise value. A definitive algorithm must, of course take into account any correlations of inherent errors; these correlations must be recognized and incorporated into the algorithm by the numerical analyst, not by the logical designer of the computer. View full abstract»

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  • Roundings in Floating-Point Arithmetic

    Page(s): 577 - 586
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    In this paper we discuss directed roundings and indicate how hardware might be designed to produce proper upward directed, downward directed, and certain commonly used symmetric roundings. Algorithms for the four binary arithmetic operations and for rounding are presented, together with proofs of their correctness; appropriate formulas for a priori error analysis of these algorithms are presented. Some of the basic applications of directed roundings are surveyed. View full abstract»

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  • A Simulative Study of Correlated Error Propagation in Various Finite-Precision Arithmetics

    Page(s): 587 - 597
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    The accumulated roundoff error incurred in long arithmetic computations involving a randomized mixture of addition, subtraction, multiplication, and division operations applied to an initial randomly generated data base is studied via simulation. Truncated and rounded floating-point arithmetic and truncated and rounded logarithmic arithmetic are simultaneously utilized for each of the computation sequences and the resulting roundoff error accumulations for these four systems are compared. The nature of the correlated errors incurred under various arithmetic operator mixes are discussed. View full abstract»

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  • Static and Dynamic Numerical Characteristics of Floating-Point Arithmetic

    Page(s): 598 - 601
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    The appearance of hexadecimal floating-point arithmetic systems has prompted a continuing discourse on the relative numerical merits of various choices of base. Until lately this discourse has centered around the static properties of the floating-point representation of numbers, and has primarily concerned only binary and hexadecimal representations. Recent events may change this discourse considerably. A third numerically attractive alternative for the choice of base has been proposed, and a comparison of the dynamic numerical properties of floating-point arithmetic systems has been completed. This paper surveys these recent events and summarizes our current knowledge of the numerical characteristics of floating-point arithmetic systems. View full abstract»

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  • On the Precision Attainable with Various Floating-Point Number Systems

    Page(s): 601 - 607
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    For scientific computations on a digital computer the set of real numbers is usually approximated by a finite set F of ``floating-point'' numbers. We compare the numerical accuracy possible with different choices of F having approximately the same range and requiring the same word length. In particular, we compare different choices of base (or radix) in the usual floating-point systems. The emphasis is on the choice of F, not on the details of the number representation or the arithmetic, but both rounded and truncated arithmetic are considered. Theoretical results are given, and some simulations of typical floating-point computations (forming sums, solving systems of linear equations, finding eigenvalues) are described. If the leading fraction bit of a normalized base-2 number is not stored explicitly (saving a bit), and the criterion is to minimize the mean square roundoff error, then base 2 is best. If unnormalized numbers are allowed, so the first bit must be stored explicitly, then base 4 (or sometimes base 8) is the best of the usual systems. View full abstract»

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  • A Combinatoric Division Algorithm for Fixed-Integer Divisors

    Page(s): 608 - 610
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    A procedure is presented for performing a combinatoric fixed-integer division that satisfies the division algorithm in regard to both quotient and remainder. In this procedure, division is performed by multiplying the dividend by the reciprocal of the divisor. The reciprocal is, in all nontrivial cases, of necessity a repeating binary fraction, and two treatments for finding the product of an integer and repeating binary fraction are developed. Two examples of the application of the procedure are given. View full abstract»

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  • A Unified Approach to the Evaluation of a Class of Replacement Algorithms

    Page(s): 611 - 618
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    The replacement problem arises in computer system management whenever the executable memory space available is insufficient to contain all data and code that may be accessed during the execution of an ensemble of programs. An example of this is the page replacement problem in virtual memory computers. The problem is solved by using a replacement algorithm that selects code or data items that are to be removed from executable memory whenever new items must be brought in and no more free storage space remains. An automaton theoretic model of replacement algorithms is introduced for the class of ``random partially preloaded'' replacement algorithms, which contain certain algorithms of practical and theoretical interest. An analysis of this class is provided in order to evaluate their performance, using the assumption that the references to the items to be stored are identically distributed independent random variables. With this model, it is shown that the well-known page replacement algorithms FIFO and RAND yield the same long-run page-fault rates. View full abstract»

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  • Circuit Structure and Switching Function Verification

    Page(s): 618 - 625
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    A new approach is presented for the design of multiple fault detection tests in which the structure of a combinational circuit is used to reduce the number of input combinations required. The structure is defined by the interconnection of the basic elements, each of arbitrary complexity. The fault model assumes that the functions realized by the basic elements may undergo any deviation whatsoever, but that the circuit structure is fault free. Thus, arbitrary combinations of multiple faults within one or more basic elements are included in the model. Decomposition theory can be used to verify that a set of input combinations is a multiple fault detection test set under this model. A process called expansion will be introduced to simplify this task. A well-defined procedure is given for deriving a suitable test set which for some circuits is minimal or near minimal. It will yield a multiple fault detection test of length less than 2n for any circuit with a nontrivial nondisjoint decomposition, defined by a basic-element partition. Higher order basic-element partitions are introduced as a generalization. An upper bound is given on the length of a multiple fault detection test for any circuit with a given structure, independent of the function realized on the structure. The bound is tighter when function information is also used. View full abstract»

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  • A Note on Conditional-Sum Addition for Base - 2 Systems

    Page(s): 626
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    Conditional-sum addition in a -2 base system and its comparison with normal binary conditional-sum addition is discussed. It is found that approximately 2.0 to 2.5 times as much hardware is required for this high-speed addition method in the negative binary system as compared to the positive binary system. View full abstract»

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  • Comments on "Decomposition Method of Determining Maximum Compatibles

    Page(s): 627
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    Some comments are made on the above note,1 to indicate that the decomposition relations used in this technique can be obtained in a much simpler way and to point out that the technique has been mentioned earlier in the literature. View full abstract»

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  • Authors' reply

    Page(s): 627
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    First Page of the Article
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  • Book Reviews

    Page(s): 628
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  • Information for authors

    Page(s): nil2
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  • [Front cover]

    Page(s): c2
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Albert Y. Zomaya
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albert.zomaya@sydney.edu.au