# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 25 of 29
• ### [Front cover]

Publication Year: 1972, Page(s): c1
| PDF (416 KB)
• ### IEEE Computer Society

Publication Year: 1972, Page(s): nil1
| PDF (233 KB)
• ### [Breaker page]

Publication Year: 1972, Page(s): nil1
| PDF (233 KB)
• ### Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication

Publication Year: 1972, Page(s):837 - 847
Cited by:  Papers (42)  |  Patents (10)
| | PDF (1528 KB)

With the increasing availability of high-speed multiplication units in large computers it is attractive to develop an iterative procedure to compute division and square root, using multiplication as the primary operation. In this paper, we present three new methods of performing square rooting rapidly which utilize multiplication and no division. Each algorithm is considered for convergence rate, ... View full abstract»

• ### A Rectangular Logic Array

Publication Year: 1972, Page(s):848 - 857
Cited by:  Papers (35)  |  Patents (6)
| | PDF (1514 KB)

A rectangular logic array is described that can realize any combinational switching function. Straightforward analysis and synthesis procedures are described and the realizations of a number of special functions are given. These include threshold functions, parity functions, symmetric functions, and universal logic functions. Other properties of the array which are examined include diagnostic proc... View full abstract»

• ### A New Representation for Faults in Combinational Digital Circuits

Publication Year: 1972, Page(s):858 - 866
Cited by:  Papers (74)
| | PDF (1817 KB)

A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including a... View full abstract»

• ### Fault-Tolerant Computers Using Dotted Logic'' Redundancy Techniques

Publication Year: 1972, Page(s):867 - 871
Cited by:  Papers (15)  |  Patents (1)
| | PDF (996 KB)

A new redundancy technique termed dotted logic is presented. Critical input errors are eliminated by joining together the output of NAND gates and NOR gates. The remaining subcritical errors are corrected by introducing redundant inputs to each logic element. Two different schemes, dotted alternating and dotted identical, are described and compared with existing error-correcting techniques. It is ... View full abstract»

• ### Fast Hybrid Computer Implementation of the Dynostat Algorithm

Publication Year: 1972, Page(s):872 - 880
Cited by:  Papers (5)
| | PDF (1600 KB)

In optimal resource allocation problems the Dynostat algorithm separates the overall optimization task into less complicated optimum seeking techniques working in parallel. A hybrid computer implementation is shown to provide a much faster optimizer than was previously the case using a digital computer. Solution accuracies are considered adequate for many practical applications. The improved formu... View full abstract»

• ### Pipelining of Arithmetic Functions

Publication Year: 1972, Page(s):880 - 886
Cited by:  Papers (25)  |  Patents (10)
| | PDF (1340 KB)

Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency. A definition of efficiency was derived to compare the relative merits of various algorithms and implementations for addition and multiplication. This definition is basically defined as bandwidth cost. Previous comparisons of adders and multipliers have generally been based on latency... View full abstract»

• ### Analysis and Compensation of High-Speed Electronic Analog-Computer Errors

Publication Year: 1972, Page(s):886 - 891
Cited by:  Papers (1)
| | PDF (987 KB)

The bandwidth limitations of the practical analog-computer units lead to dynamic errors in the computer solution. These errors can be represented either as a slight shift in the root positions of the system characteristic equation or as perturbations in the constant coefficients of the differential equation under solution. In this note, the authors report a unified approach to combine these two re... View full abstract»

• ### Notes on the Arithmetic BN Modulo A Codes

Publication Year: 1972, Page(s):891 - 894
| | PDF (755 KB)

Properties of arithmetic norms of integers are applied to the study of arithmetic BN modulo A codes. Some new properties of such codes are established. Bounds on the size of such codes are derived and an efflcient algorithm for finding the optimal single and double error-correcting BN modulo A codes is developed. View full abstract»

• ### New Results for Rado's Sigma Function for Binary Turing Machines

Publication Year: 1972, Page(s):894 - 896
Cited by:  Papers (1)
| | PDF (591 KB)

A computer program was written and executed to search for better lower bounds to Rado's noncomputable sigma and shift functions for binary Turing machines. Former results in this search (called by Rado the Busy Beaver logical game) are reviewed and new bounds found by this program are presented. View full abstract»

• ### A Flexible Rate Multiplier Circuit with Uniform Pulse Distribution Outputs

Publication Year: 1972, Page(s):896 - 899
Cited by:  Papers (5)  |  Patents (1)
| | PDF (715 KB)

In digital integrated circuits (IC's) a synchronous binary-rate multiplier is commercially available, generating a programmable number of output pulses during each internal counting cycle having a length equal to a power of two. These output pulses are not equally divided over that fixed internal counting cycle and the generated binary rate has a fixed denominator. In this note a new type of binar... View full abstract»

• ### On the Bandwidth and Interference in Interleaved Memory Systems

Publication Year: 1972, Page(s):899 - 901
Cited by:  Papers (31)
| | PDF (527 KB)

A model to estimate the bandwidth and interference in an interleaved memory system in a multiprocessor system is described. The model allows queuing on busy modules, and the results obtained show that previous results are rather pessimistic. View full abstract»

• ### A Segmentation Technique for Waveform Classification

Publication Year: 1972, Page(s):901 - 904
Cited by:  Papers (6)
| | PDF (876 KB)

This note describes the determination of waveform segments which contain the information necessary for classification. The method is successful in discriminating between the vibration record of internal combustion engines before and after repair. View full abstract»

• ### A Clustering Heuristic for Line-Drawing Analysis

Publication Year: 1972, Page(s):904 - 911
Cited by:  Papers (3)
| | PDF (1266 KB)

Certain arrangements of local features in a scene tend to group together and to be seen as units. It is suggested that, in some instances, this phenomenon might be interpretable as a process of cluster detection in a graph-structured space derived from the scene. This idea is illustrated using a class of line-drawing scenes'' that contain only horizontal and vertical line segments. View full abstract»

• ### A Relationship Between Output Symbol Occurrence Rate and Observability of Autonomous Machines

Publication Year: 1972, Page(s):911 - 913
Cited by:  Papers (1)
| | PDF (585 KB)

A bound is derived on the number of low-weight sequences an L-step observable nonsingular-autonomous finite-state machine is capable of producing. View full abstract»

• ### An Approach for the Synthesis of Multithreshold Threshold Elements

Publication Year: 1972, Page(s):913 - 920
| | PDF (1247 KB)

A new approach for the realization of multithreshold threshold elements is presented. The procedure is based on the fact that the excitations at contradictory vertices of the switching function must be unequal. The weights of the multithreshold element, in general, satisfy simple relations of the form U·W = 0, where U=(u1, u2, ... , un) and W=(w1, w... View full abstract»

• ### Digital Multiplexing Analog Signals

Publication Year: 1972, Page(s): 920
| | PDF (166 KB)

A method is presented that combines the multiplexing and A/D function to eliminate analog multiplexing switches. View full abstract»

• ### An Iterative Array for Multiplication of Signed Binary Numbers

Publication Year: 1972, Page(s):921 - 922
Cited by:  Papers (4)  |  Patents (1)
| | PDF (1145 KB)

A simple method for the implementation of Booth's algorithm for multiplication of signed binary numbers has been presented. It has been shown that for large word lengths, a significant economy has been achieved compared to Majithia and Kitai's method. View full abstract»

• ### Correction to "Batch-Fabricated Three-Dimensional Planar Coaxial Interconnections for Microelectronic Systems"

Publication Year: 1972, Page(s): 922
| | PDF (957 KB)

First Page of the Article
View full abstract»

• ### Contributors

Publication Year: 1972, Page(s):922 - 923
| PDF (1723 KB)
• ### Book Reviews

Publication Year: 1972, Page(s): 924
| PDF (258 KB)
• ### Abstracts of Current Computer Literature

Publication Year: 1972, Page(s):925 - 934
| PDF (2603 KB)
• ### Descriptor-in-Context Index

Publication Year: 1972, Page(s):935 - 938
| PDF (832 KB)

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org