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Computers, IEEE Transactions on

Issue 8 • Date Aug. 1972

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Displaying Results 1 - 25 of 29
  • [Front cover]

    Publication Year: 1972 , Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1972 , Page(s): nil1
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  • [Breaker page]

    Publication Year: 1972 , Page(s): nil1
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  • Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication

    Publication Year: 1972 , Page(s): 837 - 847
    Cited by:  Papers (30)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1528 KB)  

    With the increasing availability of high-speed multiplication units in large computers it is attractive to develop an iterative procedure to compute division and square root, using multiplication as the primary operation. In this paper, we present three new methods of performing square rooting rapidly which utilize multiplication and no division. Each algorithm is considered for convergence rate, efficiency, and implementation. The most typical and efficient one of the already-known algorithms which utilizes multiplication, here called the N algorithm, is introduced for the purpose of comparison with the new algorithms. The effect and importance of the initial approximation is considered. (One of the algorithms, here called the G algorithm, is described in detail with the emphasis on its high efficiency.) View full abstract»

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  • A Rectangular Logic Array

    Publication Year: 1972 , Page(s): 848 - 857
    Cited by:  Papers (25)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1514 KB)  

    A rectangular logic array is described that can realize any combinational switching function. Straightforward analysis and synthesis procedures are described and the realizations of a number of special functions are given. These include threshold functions, parity functions, symmetric functions, and universal logic functions. Other properties of the array which are examined include diagnostic procedures, isolating defective cells, bounds on the array size, and possible implementations of the basic cell. View full abstract»

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  • A New Representation for Faults in Combinational Digital Circuits

    Publication Year: 1972 , Page(s): 858 - 866
    Cited by:  Papers (69)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1817 KB)  

    A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including all two-level single-output circuits, it is shown that the detection of all single faults implies the detection of all multiple faults. The behavior of any circuit under fault conditions is represented in terms of the classes of indistinguishable faults. This results in a description of the faulty circuit by means of Boolean equations that are readily manipulated for the purpose of fault simulation or test generation. A connection graph interpretation of this fault representation is discussed. Heuristic methods for the selection of efficient tests without extensive computation are derived from these connection graphs. View full abstract»

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  • Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques

    Publication Year: 1972 , Page(s): 867 - 871
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    A new redundancy technique termed dotted logic is presented. Critical input errors are eliminated by joining together the output of NAND gates and NOR gates. The remaining subcritical errors are corrected by introducing redundant inputs to each logic element. Two different schemes, dotted alternating and dotted identical, are described and compared with existing error-correcting techniques. It is shown that these new methods have several advantages over quadded or triple modular redundancy (TMR) networks. In addition to correcting single faults, dotted schemes are easily extended to cover multiple faults. Methods for initial failure determinations for dotted schemes are proposed. Finally, it is shown that a network consisting of complex function elements can be made more reliable by dotting. View full abstract»

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  • Fast Hybrid Computer Implementation of the Dynostat Algorithm

    Publication Year: 1972 , Page(s): 872 - 880
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1600 KB)  

    In optimal resource allocation problems the Dynostat algorithm separates the overall optimization task into less complicated optimum seeking techniques working in parallel. A hybrid computer implementation is shown to provide a much faster optimizer than was previously the case using a digital computer. Solution accuracies are considered adequate for many practical applications. The improved formulation presented of gradient search is advantageous for high-speed optimization. Confidence is increased in analog computer solutions by introducing auxiliary algorithms that check on solution feasibility and also improve accuracy. View full abstract»

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  • Pipelining of Arithmetic Functions

    Publication Year: 1972 , Page(s): 880 - 886
    Cited by:  Papers (23)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1340 KB)  

    Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency. A definition of efficiency was derived to compare the relative merits of various algorithms and implementations for addition and multiplication. This definition is basically defined as bandwidth cost. Previous comparisons of adders and multipliers have generally been based on latency. In a pipeline environment, latency (or its inverse bandwidth) is not as important. Any bandwidth is possible up to the physical limitations on gate delay variations and pulse skew. The formal definition for efficiency is efficiency = N/D·G where N is the number of bits in the operands, D is the delay (uniform) of each pipeline stage in units of gate delays, and G is the total number of gates, including any used for latching. In cases where gate variations and pulse skewing are well defined, pipelining using the Earle latch results in increased efficiency. The most efficient adder is a maximally pipelined conditional-sum adder (three stages with a delay of four gates per stage). Its efficiency is 6.30×10-3. The most efficient multiplier is a maximally pipelined tree multiplier (eight stages with a delay of four gates per stage). Its efficiency is 3.48×10-4. View full abstract»

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  • Analysis and Compensation of High-Speed Electronic Analog-Computer Errors

    Publication Year: 1972 , Page(s): 886 - 891
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (987 KB)  

    The bandwidth limitations of the practical analog-computer units lead to dynamic errors in the computer solution. These errors can be represented either as a slight shift in the root positions of the system characteristic equation or as perturbations in the constant coefficients of the differential equation under solution. In this note, the authors report a unified approach to combine these two representations of dynamic errors and also show that these errors can be compensated for by setting the system after initial perturbations in its constant coefficients and in its driving functions have occurred. The approach is generalized for a system of simultaneous linear differential equations with constant coefficients. This technique will be of value in achieving a reasonable degree of accuracy with relatively inexpensive analog-computer components, and in extending the range of operating frequencies for a certain specified accuracy. View full abstract»

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  • Notes on the Arithmetic BN Modulo A Codes

    Publication Year: 1972 , Page(s): 891 - 894
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (755 KB)  

    Properties of arithmetic norms of integers are applied to the study of arithmetic BN modulo A codes. Some new properties of such codes are established. Bounds on the size of such codes are derived and an efflcient algorithm for finding the optimal single and double error-correcting BN modulo A codes is developed. View full abstract»

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  • New Results for Rado's Sigma Function for Binary Turing Machines

    Publication Year: 1972 , Page(s): 894 - 896
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (591 KB)  

    A computer program was written and executed to search for better lower bounds to Rado's noncomputable sigma and shift functions for binary Turing machines. Former results in this search (called by Rado the Busy Beaver logical game) are reviewed and new bounds found by this program are presented. View full abstract»

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  • A Flexible Rate Multiplier Circuit with Uniform Pulse Distribution Outputs

    Publication Year: 1972 , Page(s): 896 - 899
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (715 KB)  

    In digital integrated circuits (IC's) a synchronous binary-rate multiplier is commercially available, generating a programmable number of output pulses during each internal counting cycle having a length equal to a power of two. These output pulses are not equally divided over that fixed internal counting cycle and the generated binary rate has a fixed denominator. In this note a new type of binary-rate multiplier is described. This circuit allows the programming of both numerator a and denominator b of the rate of the numbers of output and input pulses. It operates in such a way that during a cycle of b pulses the circuit output generates a number of pulses divided over the cycle of b pulses as equally divided as is possible in digital systems. View full abstract»

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  • On the Bandwidth and Interference in Interleaved Memory Systems

    Publication Year: 1972 , Page(s): 899 - 901
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (527 KB)  

    A model to estimate the bandwidth and interference in an interleaved memory system in a multiprocessor system is described. The model allows queuing on busy modules, and the results obtained show that previous results are rather pessimistic. View full abstract»

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  • A Segmentation Technique for Waveform Classification

    Publication Year: 1972 , Page(s): 901 - 904
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB)  

    This note describes the determination of waveform segments which contain the information necessary for classification. The method is successful in discriminating between the vibration record of internal combustion engines before and after repair. View full abstract»

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  • A Clustering Heuristic for Line-Drawing Analysis

    Publication Year: 1972 , Page(s): 904 - 911
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1266 KB)  

    Certain arrangements of local features in a scene tend to group together and to be seen as units. It is suggested that, in some instances, this phenomenon might be interpretable as a process of cluster detection in a graph-structured space derived from the scene. This idea is illustrated using a class of line-drawing ``scenes'' that contain only horizontal and vertical line segments. View full abstract»

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  • A Relationship Between Output Symbol Occurrence Rate and Observability of Autonomous Machines

    Publication Year: 1972 , Page(s): 911 - 913
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (585 KB)  

    A bound is derived on the number of low-weight sequences an L-step observable nonsingular-autonomous finite-state machine is capable of producing. View full abstract»

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  • An Approach for the Synthesis of Multithreshold Threshold Elements

    Publication Year: 1972 , Page(s): 913 - 920
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1247 KB)  

    A new approach for the realization of multithreshold threshold elements is presented. The procedure is based on the fact that the excitations at contradictory vertices of the switching function must be unequal. The weights of the multithreshold element, in general, satisfy simple relations of the form U·W = 0, where U=(u1, u2, ... , un) and W=(w1, w2, ... , wn) such that ui ¿{1,0, ¿1,}, i=1,2, ... n, and W¿In. Comparison of the excitations E(Xi) = W·Xi and E(Xj) = W·XjM at TRUE, and FALSE vertices Xi and Xj, respectively, for all specified vertices reusult in some inequalities of the form U·W¿0. Subsets of the remaining set of weight expressions U·W that are compatible are then determined, i.e., no linear combination of some or all of these expressions results in an expression Ui·W such that Ui·W¿0 and independent of each other. Each expression of each of these subsets is then equated to zero, and simple relations between weights are established. These are then used to find the weights vectors W's. The threshold vector T for each W is next established. From the set of weight-threshold vectors (W, T) the desired solution is determined by some minimality criterion. An example has been worked out by hand and an algorithm is given for systematic synthesis procedure. View full abstract»

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  • Digital Multiplexing Analog Signals

    Publication Year: 1972 , Page(s): 920
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    A method is presented that combines the multiplexing and A/D function to eliminate analog multiplexing switches. View full abstract»

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  • An Iterative Array for Multiplication of Signed Binary Numbers

    Publication Year: 1972 , Page(s): 921 - 922
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1145 KB)  

    A simple method for the implementation of Booth's algorithm for multiplication of signed binary numbers has been presented. It has been shown that for large word lengths, a significant economy has been achieved compared to Majithia and Kitai's method. View full abstract»

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  • Correction to "Batch-Fabricated Three-Dimensional Planar Coaxial Interconnections for Microelectronic Systems"

    Publication Year: 1972 , Page(s): 922
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    First Page of the Article
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  • Contributors

    Publication Year: 1972 , Page(s): 922 - 923
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    Freely Available from IEEE
  • Book Reviews

    Publication Year: 1972 , Page(s): 924
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    Freely Available from IEEE
  • Abstracts of Current Computer Literature

    Publication Year: 1972 , Page(s): 925 - 934
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  • Descriptor-in-Context Index

    Publication Year: 1972 , Page(s): 935 - 938
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org