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IEEE Transactions on Computers

Issue 1 • Jan. 1970

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Displaying Results 1 - 22 of 22
  • [Front cover]

    Publication Year: 1970, Page(s): c1
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  • IEEE Computer Group

    Publication Year: 1970, Page(s): nil1
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  • [Breaker page]

    Publication Year: 1970, Page(s): nil1
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  • The Extended Resolution Digital Differential Analyzer: A New Computing Structure for Solving Differential Equations

    Publication Year: 1970, Page(s):1 - 9
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1553 KB)

    In conventional digital differential analyzers (DDA), the word length used for the transmission of information between integrators is restricted to at most a single magnitude bit and a sign bit. This restriction seriously limits integrator frequency response and has to a large extent been responsible for the failure of DDAs to achieve widespread acceptance as general purpose differential analyzers... View full abstract»

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  • An Interactive Computer Approach to Tolerance Analysis

    Publication Year: 1970, Page(s):10 - 16
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2365 KB)

    An interactive technique for statistical tolerance analysis has been developed for a computer with graphic display. The computer program called TAP provides for random perturbation of parameter values, repeated evaluation of system performance, and display of distribution histograms. The interactive capability of the program enables the designer to introduce modifications to the system so that the... View full abstract»

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  • A Generalized Technique for Spectral Analysis

    Publication Year: 1970, Page(s):16 - 25
    Cited by:  Papers (77)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1483 KB)

    A technique is presented to implement a class of orthogonal transformations on the order of pN logp N operations. The technique is due to Good [1] and implements a fast Fourier transform, fast Hadamard transform, and a variety of other orthogonal decompositions. It is shown how the Kronecker product can be mathematically defined and efficiently implemented using a matrix factorization m... View full abstract»

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  • Computer Simulation of Pulse Propagation Through a Periodic Loaded Transmission Line

    Publication Year: 1970, Page(s):25 - 33
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1710 KB)

    In view of the speed of today's hardware components, wirings between IC pins cannot be regarded as ``short circuit jumper+some C'' but should be treated as a piece of transmission line. The central problem in design of any equipment employing a number of IC is thus to predict the extent of gradual deterioration of waveforms as pulses propagate along a length of transmission line loaded with many l... View full abstract»

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  • An Error-Detecting Binary Adder: A Hardware-Shared Implementation

    Publication Year: 1970, Page(s):34 - 38
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (881 KB)

    A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes m... View full abstract»

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  • A Scheme for Synchronizing High-Speed Logic: Part I

    Publication Year: 1970, Page(s):39 - 47
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1712 KB)

    In this paper we concern ourselves with the problem of obtaining high sequence rate sequential machines; machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devi... View full abstract»

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  • The Organization of High-Speed Memory for Parallel Block Transfer of Data

    Publication Year: 1970, Page(s):47 - 53
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1521 KB)

    This paper describes the organization of a multi-module memory, designed to facilitate parallel block transfers. All modules are assumed to be identical, and the individual modules can fetch or store no more than one word or word group during any single memory cycle. Parallel block transfers are made possible in multimodule memories by utilizing a device called the memory circulator and by organiz... View full abstract»

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  • Iteratively Realized Sequential Circuits

    Publication Year: 1970, Page(s):54 - 66
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1741 KB)

    Synthesis techniques are presented for realizing an arbitrary synchronous flow table in the form of an array of identical modules interconnected in a regular pattern. Several types of structures and their corresponding modules are considered, and a relationship between these structures and earlier work on combinational circuits is shown. View full abstract»

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  • Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part II

    Publication Year: 1970, Page(s):66 - 73
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1717 KB)

    This paper is Part II of a two-part study of systematic procedures for realizing synchronous sequential machines using flip-flop memory. In this study the methods of Dolotta and McCluskey, and Weiner and Smith are generalized so that they can be used to obtain directly good realizations of machines using flip-flop memory. In Part I the generalizations were simple, straightforward, and required a m... View full abstract»

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  • A Logic-in-Memory Computer

    Publication Year: 1970, Page(s):73 - 78
    Cited by:  Papers (29)  |  Patents (65)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1461 KB)

    If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described th... View full abstract»

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  • A Modified Matrix Algorithm for Determining the Complete Connection Matrix of a Switching Network

    Publication Year: 1970, Page(s):78 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (457 KB)

    An efficient matrix algorithm is described which enables one to determine the complete connection matrix in only two steps. View full abstract»

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  • A Simple Convergent Algorithm for Rapid Solution of Polynomial Equations

    Publication Year: 1970, Page(s):79 - 80
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Extensions to a straightforward, always convergent method for solving polynomial equations given in a previous paper are considered. The extensions consist of additional simple calculations and logic instructions which considerably improve convergence rate for the cases when multiple roots exist or when roots are close together. It is believed that in terms of simplicity and convergence properties... View full abstract»

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  • Mathematical ``Lower Bounds'' and the Logic Circuit Designer

    Publication Year: 1970, Page(s):80 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB)

    The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder. View full abstract»

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  • Contributors

    Publication Year: 1970, Page(s):82 - 84
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  • Abstracts of Current Computer Literature

    Publication Year: 1970, Page(s):85 - 94
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  • Descriptor-in-Context Index

    Publication Year: 1970, Page(s):94 - 99
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  • Identifier index

    Publication Year: 1970, Page(s):99 - 100
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  • Author index

    Publication Year: 1970, Page(s): 100
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  • Information for authors

    Publication Year: 1970, Page(s): nil2
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org