# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 25 of 31
• ### [Front cover]

Publication Year: 1968, Page(s): c1
| PDF (477 KB)
• ### IEEE Computer Group

Publication Year: 1968, Page(s): nil1
| PDF (169 KB)
• ### [Breaker page]

Publication Year: 1968, Page(s): nil1
| PDF (169 KB)
• ### Editor's notice [Transactions name change]

Publication Year: 1968, Page(s): 1
| PDF (39 KB)
• ### An Iteratively Structured General-Purpose Digital Computer

Publication Year: 1968, Page(s):2 - 9
Cited by:  Papers (4)
| | PDF (1537 KB)

A general-purpose synchronous stored-program digital computer is described. The computer is composed solely of many small, identically structured sequential machines, each machine having fewer than 211 states. The one-dimensional iterative array of sequential machines, or cells, which constitutes this computer is similar to the distributed logic associative memory originally proposed by... View full abstract»

• ### Asynchronous Operation of an Iteratively Structured General-Purpose Digital Computer

Publication Year: 1968, Page(s):10 - 17
| | PDF (1298 KB)

The preceding paper proposed a general-purpose digital computer structure consisting of many small iteratively connected sequential machines. A set of machine instructions was presented and a programming example of synchronous machine operation was given. This paper examines some of the problems associated with asynchronous operation of this iteratively structured digital computer. A solution is p... View full abstract»

• ### Definite Asynchronous Sequential Circuits

Publication Year: 1968, Page(s):18 - 26
Cited by:  Papers (7)
| | PDF (1498 KB)

An asynchronous unit delay is an n input n output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining when a fundamental mode flow table is realizable as a feedback-free connection of asynchronous unit delays. It is shown that such a realization ex... View full abstract»

• ### A Mathematical Model of Finite Random Sequential Automata

Publication Year: 1968, Page(s):27 - 31
Cited by:  Papers (1)
| | PDF (719 KB)

The sequential logic theory previously advanced[2] is generalized to operations between variables of maximum word length n. Based on the generalized sequential logic operations, a new kind of probability, termed sequential probability, is introduced. By means of sequential probability, a mathematical model can be obtained for finite random sequential automata. This model can be used for... View full abstract»

• ### An Approach for the Realization of Multithreshold Threshold Elements

Publication Year: 1968, Page(s):32 - 46
Cited by:  Papers (6)
| | PDF (2279 KB)

An algorithm for the realization of k-threshold threshold realizable functions is presented. Instead of solving the set of linear inequalities, where the unknowns are the weights corresponding to the input variables, incremental weights are sought. The procedure reduces to that of resolving contradicting pairs of vertices by the incremental weights. The minimum number of thresholds are sought for ... View full abstract»

• ### Input Tolerance Considerations for Multithreshold Threshold Elements

Publication Year: 1968, Page(s):46 - 54
| | PDF (1357 KB)

This paper deals with input tolerance considerations of a multithreshold threshold element. The concept of a multilevel minus-plus-one model[9] of a threshold element is introduced. It is shown that the multilevel minus-plus-one model is equivalent to the zero-one model[9] of a multithreshold element. The equivalence is established through a set of defining equations similar ... View full abstract»

• ### An Analog Comparator as a Pseudo-Light Pen for Computer Displays

Publication Year: 1968, Page(s):54 - 55
Cited by:  Papers (3)
| | PDF (455 KB)

An Analog Comparator Interrupt Device signals the computer central processor whenever the computer display unit deflection voltages cause the CRT beam to fall within a small square surrounding a previously specified display coordinate. This provides the display with the sensing capability of a light pen that is necessary if a RAND tablet or other position input device is to be used to point at dis... View full abstract»

• ### On Equivalence of State Assignments

Publication Year: 1968, Page(s):55 - 57
Cited by:  Papers (3)
| | PDF (598 KB)

Using a new definition for the equivalent of state assignments, the number of nonequivalent state assignments is derived. The exact number of nondegenerate state assignments is also compted. View full abstract»

• ### Generation of Self-Dual and Self-Complementary Dual Functions

Publication Year: 1968, Page(s):57 - 66
Cited by:  Papers (1)
| | PDF (1446 KB)

Properties of self-dual and self-complementary dual functions are discussed. Necessary and sufficient conditions of self-dual and self-complementary dual functions are obtained in terms of the multithreshold weight threshold vector. In particular, self-dual and self-complementary dual functions are shown to be realizable only by an odd and even number of effective thresholds, respectively. A thres... View full abstract»

Publication Year: 1968, Page(s):66 - 67
Cited by:  Papers (4)
| | PDF (469 KB)

This paper discusses ternary cellular cascades, i.e., one-dimensional arrays of ternary two-input one-output cells. It is shown that every ternary combinational switching function can be realized by such a cascade. View full abstract»

• ### Maximal Memory Binary Input-Binary Output Finite-Memory Sequential Machines

Publication Year: 1968, Page(s):67 - 71
Cited by:  Papers (7)
| | PDF (796 KB)

Gill[1] has shown that if there exists a finite-memory n-state sequential machine with finite memory μ, then μ cannot exceed ½n(n-1)ΔNn. He has further shown[2] that there exists an n-state Nn input-binary output machine with memory μ= Nn for every n. The question of whether a tighter upper bound might b... View full abstract»

• ### A Partitioning Method for Combinational Synthesis

Publication Year: 1968, Page(s):72 - 75
Cited by:  Papers (3)
| | PDF (878 KB)

A method of network synthesis for general combinational functions that uses a number of fixed threshold logic units not greatly in excess of the theoretical minimum is described. It can be used with adaptive logic in which case a minority of the interconnections are simply adapted once according to the rule originally suggested by Hebb. This network on its own has no capacity for generalization,... View full abstract»

• ### Symmetry Types in Threshold Logic

Publication Year: 1968, Page(s):75 - 78
| | PDF (892 KB)

The idea of similarity'' between threshold functions is developed in a unified fashion and illustrated geometrically. Formulas are given to transform the corresponding threshold gate realizations. View full abstract»

• ### An Adaptive Threshold Logic Gate Using Capacitive Analog Weights

Publication Year: 1968, Page(s):78 - 81
Cited by:  Papers (3)
| | PDF (853 KB)

A physical realization of an adaptive threshold logic gate which can be used to realize linearly separable switching functions is presented. The system is completely electronic and is easily implemented in the sense that standard components may be used throughout. The memory circuit used for each weight of the device stabilizes the voltage across a capacitor by means of a sampling technique. Over ... View full abstract»

• ### DDA Scaling Graph

Publication Year: 1968, Page(s):81 - 84
Cited by:  Papers (2)
| | PDF (864 KB)

Finite graph theory is applied to the problem of scaling fixed point Digital Differential Analyzers. The DDA scaling graph is introduced as a representation of the essential scaling information rather than the conventional integrator servo program network. Using the scaling graph, optimal scales are obtained simply, by constructing a maximum distance tree. View full abstract»

• ### A Combination Hardware-Software Debugging System

Publication Year: 1968, Page(s):84 - 86
Cited by:  Papers (1)  |  Patents (4)
| | PDF (733 KB)

A scheme is proposed for automatically detecting many programming errors; in particular, those errors which can cause a program to misbehave in different ways, depending upon how the faulty program and its data are mapped into storage. Error detection is accomplished by simultaneously running two versions of a program which purport to be logically identical, with appropriate hardware checking betw... View full abstract»

• ### A Simple Probability Model Yielding Performance Bounds for Modular Memory Systems

Publication Year: 1968, Page(s):86 - 89
Cited by:  Papers (2)
| | PDF (835 KB)

A simple probability model is defined that represents modular memory systems under saturation demand for storage. An analysis of the model based on the theory of finite Markov chains leads to results that demonstrate the effects of changes in loading times and the number of modules on system performance. View full abstract»

• ### The Simulation of Variable Delay

Publication Year: 1968, Page(s):89 - 94
Cited by:  Papers (5)
| | PDF (1964 KB)

A dual classification of variable delays 1) by their explicit dependence on time or through a state variable and 2) through their origins as pipe'' or nonpipe'' problems is presented. Techniques of simulation through standard analog components and, more particularly, transport devices are analyzed and further classification made of the latter to distinguish those suitable for state-variable de... View full abstract»

• ### On the Cascade Decomposition of Prefix Automata

Publication Year: 1968, Page(s):94 - 95
Cited by:  Papers (2)
| | PDF (1139 KB)

Perles, Rabin and Shamir conceived prefix automata as realizations of k-definite deterministic automata. The structure theory of deterministic automata as developed by Zeiger reveals that a prefix automaton may be decomposed into a cascade of reset machines. View full abstract»

• ### On Dolotta-McCluskey Technique

Publication Year: 1968, Page(s): 95
| | PDF (865 KB)

First Page of the Article
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• ### Contributors

Publication Year: 1968, Page(s):95 - 96
| PDF (1730 KB)

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org