By Topic

IEEE Design & Test of Computers

Issue 4 • Nov. 1984

Filter Results

Displaying Results 1 - 25 of 35
  • Front Cover

    Publication Year: 1984, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • [Advertisement]

    Publication Year: 1984, Page(s):2 - 3
    Request permission for commercial reuse | PDF file iconPDF (1280 KB)
    Freely Available from IEEE
  • IEEE Design&Test of Computers

    Publication Year: 1984, Page(s): 4
    Request permission for commercial reuse | PDF file iconPDF (881 KB)
    Freely Available from IEEE
  • Tables of contents

    Publication Year: 1984, Page(s):4 - 5
    Request permission for commercial reuse | PDF file iconPDF (1828 KB)
    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1984, Page(s):4 - 5
    Request permission for commercial reuse | PDF file iconPDF (1828 KB)
    Freely Available from IEEE
  • Editorial Board

    Publication Year: 1984, Page(s): 5
    Request permission for commercial reuse | PDF file iconPDF (959 KB)
    Freely Available from IEEE
  • [Advertisement]

    Publication Year: 1984, Page(s):6 - 7
    Request permission for commercial reuse | PDF file iconPDF (2209 KB)
    Freely Available from IEEE
  • From the Editor-in-Chief

    Publication Year: 1984, Page(s): 8
    Request permission for commercial reuse | PDF file iconPDF (949 KB)
    Freely Available from IEEE
  • [Advertisement]

    Publication Year: 1984, Page(s): 9
    Request permission for commercial reuse | PDF file iconPDF (727 KB)
    Freely Available from IEEE
  • D&T Scene

    Publication Year: 1984, Page(s):10 - 14
    Request permission for commercial reuse | PDF file iconPDF (3945 KB)
    Freely Available from IEEE
  • D&T Interview

    Publication Year: 1984, Page(s):15 - 23
    Request permission for commercial reuse | PDF file iconPDF (7803 KB)
    Freely Available from IEEE
  • [Advertisement]

    Publication Year: 1984, Page(s): 23
    Request permission for commercial reuse | PDF file iconPDF (182 KB)
    Freely Available from IEEE
  • [Advertisement]

    Publication Year: 1984, Page(s): 24
    Request permission for commercial reuse | PDF file iconPDF (121 KB)
    Freely Available from IEEE
  • Design for Testability for Complete Test Coverage

    Publication Year: 1984, Page(s):25 - 32
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7366 KB)

    Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achie... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The electronic workstation-an overview

    Publication Year: 1984, Page(s):33 - 41
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7772 KB)

    The computer-aided engineering workstation is growing at an extremely rapid rate, in both market and technological advance. While even the earliest systems were valuable to designers and managers, the second generation is a quantum leap ahead in accommodating the real on-the-job needs of the designer. Advances in sophisticated tools, the interface, I/O, and communications through the network have ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Advertisement]

    Publication Year: 1984, Page(s):41 - 44
    Request permission for commercial reuse | PDF file iconPDF (3041 KB)
    Freely Available from IEEE
  • LOCST: A Built-In Self-Test Technique

    Publication Year: 1984, Page(s):45 - 52
    Cited by:  Papers (40)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7799 KB)

    A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan'' feature, and an on-chip monitor test controller has been implemented on three VLSI chips by the IBM Federal Systems Division. This method (designated LSSD on-chip self-test, or LOCST) uses existing level-sensitive scan design strings to serially scan random test pattern... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Icon: A Tool for Design at Schematic, Virtual Grid, and Layout Levels

    Publication Year: 1984, Page(s):53 - 60
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4808 KB)

    The design of a custom VLSI chip requires work at several levels of abstraction. For example, random logic is naturally described as schematics, hand-entered layouts are naturally entered on a virtual grid, and machine-generated or compacted layouts are edited on an accurate, geometrically fixed grid. Icon is a new computer-aided design tool that allows these aspects of design to be handled simult... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Advertisement]

    Publication Year: 1984, Page(s): 61
    Request permission for commercial reuse | PDF file iconPDF (956 KB)
    Freely Available from IEEE
  • Modeling and Testing for Timing Faults in Synchronous Sequential Circuits

    Publication Year: 1984, Page(s):62 - 74
    Cited by:  Papers (73)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9299 KB)

    Even with proper design, integrated circuits and systems can have timing problems because of physical faults or variation of parameters. The authors introduce a fault model that takes into account timing related failures in both the combinational logic and the storage elements. Using their fault model and the system's requirements for proper operation, the authors propose ways to handle flipflop-t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automated Synthesis of Digital systems

    Publication Year: 1984, Page(s):75 - 81
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2886 KB)

    This tutorial describes the automatic synthesis of digital implementations from higher-level specifications. The synthesis process is described in terms of four mechanisms: resource allocation, design transformation, composition, and scheduling. These mechanisms are illustrated with examples taken from three synthesis categories: algorithm synthesis, register-transfer synthesis, and logic synthesi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Design&Test of Computers

    Publication Year: 1984, Page(s):82 - 85
    Request permission for commercial reuse | PDF file iconPDF (1793 KB)
    Freely Available from IEEE
  • Membership Application

    Publication Year: 1984, Page(s): 86
    Request permission for commercial reuse | PDF file iconPDF (624 KB)
    Freely Available from IEEE
  • Design Automation conference Roundtable: industry-university consortia fill need

    Publication Year: 1984, Page(s):87 - 93
    Request permission for commercial reuse | PDF file iconPDF (6586 KB)
    Freely Available from IEEE
  • D&T Conference

    Publication Year: 1984, Page(s):94 - 97
    Request permission for commercial reuse | PDF file iconPDF (3715 KB)
    Freely Available from IEEE

Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty