IEEE Design & Test of Computers

Issue 3 • Aug. 1984

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  • [Front cover]

    Publication Year: 1984, Page(s): c1
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  • [Advertisement]

    Publication Year: 1984, Page(s): nil1
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  • IEEE Design&Test of Computers

    Publication Year: 1984, Page(s):nil2 - nil3
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  • [Advertisement]

    Publication Year: 1984, Page(s):1 - 3
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  • IEEE Computer Society

    Publication Year: 1984, Page(s): 4
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  • Tables of contents

    Publication Year: 1984, Page(s):4 - 5
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  • [Breaker page]

    Publication Year: 1984, Page(s):4 - 5
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  • Editorial Board

    Publication Year: 1984, Page(s): 5
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  • [Advertisement]

    Publication Year: 1984, Page(s):6 - 7
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  • About the cover

    Publication Year: 1984, Page(s): 8
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  • From the Editor-in-Chief

    Publication Year: 1984, Page(s): 9
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  • D&T Scene

    Publication Year: 1984, Page(s):10 - 15
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  • [Advertisement]

    Publication Year: 1984, Page(s):16 - 17
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  • Probing the State of the Art

    Publication Year: 1984, Page(s):18 - 19
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  • [Advertisement]

    Publication Year: 1984, Page(s): 20
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  • A Survey of Hardware Accelerators Used in Computer-Aided Design

    Publication Year: 1984, Page(s):21 - 39
    Cited by:  Papers (125)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (15367 KB)

    Hardware accelerators, or special-purpose engines, have been used in computer-aided design applications for nearly 20 years. In this time, roughly 20 machines have been built and tested specifically for such purposes as simulation, design rule checking, placement, and routing. Their uses are increasing, and the machines are becoming commercially available. This survey describes not only the machin... View full abstract»

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  • [Advertisement]

    Publication Year: 1984, Page(s):40 - 42
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  • Wirability-designing wiring space for chips and chip packages

    Publication Year: 1984, Page(s):43 - 51
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4605 KB)

    Early estimation of the wiring space requirements for logic chips and chip-carrying packages is essential. The authors propose a way to do this by taking into account the average length of wiring connections, the number of logic units to be wired, and the average number of connections per logic unit. They show that the probability of automatic wiring success is a function of the number of wiring t... View full abstract»

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  • [Advertisement]

    Publication Year: 1984, Page(s): 51
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  • Exploiting Domain Knowledge in IC Cell Layout

    Publication Year: 1984, Page(s):52 - 64
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3251 KB)

    This article describes a knowledge-based expert system, Talib, whose domain of expertise is in the cell layout phase of the IC design task. It applies Al techniques and has been used to design IC layouts in the circuit range of four to 86 transistors. The system is implemented in OPS5, a general-purpose rule-based language. Talib accepts as input the schematic of the proposed circuit along with th... View full abstract»

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  • Call for Paper Proposals

    Publication Year: 1984, Page(s): 65
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  • Design Verification and Testing of the WE 32100 CPUs

    Publication Year: 1984, Page(s):66 - 75
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5206 KB)

    This article reviews the design verification and testing methods that evolved during the development of four AT&T 32-bit microprocessors. Software modeling and regression testing??without hardware breadboards??proved to be a viable approach for these high-performance CPU chips. AT&T investigated five built-in testability features: a compressed-data output pin, macro-ROM internal access, re... View full abstract»

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  • [Advertisement]

    Publication Year: 1984, Page(s): 75
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  • Characterization and Testing of Physical Failures in MOS Logic Circuits

    Publication Year: 1984, Page(s):76 - 86
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7676 KB)

    Studies indicate that the conventional stuck-at fault model is inadequate for modeling the effects of physical failures on MOS circuits. The authors illustrate various types of non-stuck-at behavior, such as indeterminate logic levels, timing errors, and alteration of logic functions. They discuss the generation of tests for detecting the failures in simple and complex MOS circuits. An advantage o... View full abstract»

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  • [Advertisement]

    Publication Year: 1984, Page(s):87 - 89
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty