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Advanced Packaging, IEEE Transactions on

Issue 2 • Date May 2009

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Displaying Results 1 - 25 of 47
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - 234
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    Freely Available from IEEE
  • IEEE Transactions on Advanced Packaging publication information

    Publication Year: 2009 , Page(s): C2
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    Freely Available from IEEE
  • Foreword Special Section on High-Speed I/O Channels

    Publication Year: 2009 , Page(s): 235 - 236
    Cited by:  Papers (1)
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    Freely Available from IEEE
  • Modeling and Analysis of High-Speed I/O Links

    Publication Year: 2009 , Page(s): 237 - 247
    Cited by:  Papers (31)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1658 KB) |  | HTML iconHTML  

    Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design. View full abstract»

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  • On-Die Power Supply Noise Measurement Techniques

    Publication Year: 2009 , Page(s): 248 - 259
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1052 KB) |  | HTML iconHTML  

    This paper presents techniques for characterizing wide-band on-chip power supply noise using only two on-chip low-throughput samplers. The properties of supply noise and their associated measurement techniques are reviewed to show how this can be achieved. An initial design of the samplers uses high-resolution VCO-based analog-to-digital converters, and experimental results from a test-chip verify the efficacy of the measurement techniques. To enable simple sampler designs to be used even in aggressively scaled process technologies, measurement systems based on dithered low-resolution samplers are also developed and experimentally characterized. View full abstract»

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  • Statistical Simulation of Physical Transmission Media

    Publication Year: 2009 , Page(s): 260 - 267
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    Predicting the performance of a high-speed serial link for real world application requires a different approach to simulation than that traditionally used in slower systems. Given target bit error rates of 10-12 and lower, the ability to statistically confirm such performance in measurement, let alone simulation is challenging. For physically realistic interconnect and feasible silicon implementations, certain assumptions allow this problem to be solved with an analytical method in the so called statistical domain. The underlying assumption made to allow the problem to be treated statistically is one of superposition, which does not exclude the ability to analyze nonlinear or time variant problems. This work initially describes the basic theory of statistical signal analysis, and the latest extensions to this theory which allow correlated jitter and data problems to be studied. Simple code implementation are given together with a real world example, to help the reader understand the mathematical analysis and its application. View full abstract»

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  • Channel Coding For High-Speed Links: A Systematic Look at Code Performance and System Simulation

    Publication Year: 2009 , Page(s): 268 - 279
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1179 KB) |  | HTML iconHTML  

    While channel coding is a standard method of improving a system's energy efficiency in digital communications, its practice does not extend to high-speed links. Increasing demands in network speeds are placing a large burden on the energy efficiency of high-speed links and render the benefit of channel coding for these systems a timely subject. The low error rates of interest and the presence of residual intersymbol interference (ISI) caused by hardware constraints impede the analysis and simulation of coded high-speed links. Focusing on the residual ISI and combined noise as the dominant error mechanisms, this paper analyzes error correlation through concepts of error region, channel signature, and correlation distance. This framework provides a deeper insight into joint error behaviors in high-speed links, extends the range of statistical simulation for coded high-speed links, and provides a case against the use of biased Monte Carlo methods in this setting. Finally, based on a hardware test bed, the performance of standard binary forward error correction and error detection schemes is evaluated, from which recommendations on coding for high-speed links are derived. View full abstract»

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  • Predicting Microwave Digital Signal Integrity

    Publication Year: 2009 , Page(s): 280 - 289
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB) |  | HTML iconHTML  

    High-speed digital signal integrity at data rates above 6 Gb/s is an obstacle to reliable serial link operation. Two signal integrity challenges include dispersion due to frequency-dependent losses and reflections created at impedance mismatches. Signal integrity analysis relies on time-domain simulation of pseudo-random data patterns. This paper explores a predictive method for interconnect eye closure caused by reflections at the transmitter and receiver and does not require extensive time domain simulation. Worst-case bounds on intersymbol interference and data-dependent jitter aid prediction for link budgets under channel variations. This method is applied to the design of a passive equalizer. View full abstract»

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  • Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond

    Publication Year: 2009 , Page(s): 290 - 297
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (674 KB) |  | HTML iconHTML  

    The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 times 10.3125 Gb/s, and 10 times10.3125 Gb/s for Ethernet 40 G/100 G), 8 times fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification. View full abstract»

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  • Frequency-Division Bidirectional Communication Over Chip-to-Chip Channels

    Publication Year: 2009 , Page(s): 298 - 305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1843 KB) |  | HTML iconHTML  

    Frequency division multiple access is applied to bidirectional communication over chip-to-chip links. Frequency division is implemented by dividing the spectrum into low-frequency (dc) and high-frequency (ac) bands using a simple LC filter. The nonidealities that this filter introduces are compensated for with a transmitter/receiver pair that can recover signals in both bands. The receiver uses a dual-path topology that includes hysteresis to recover data from a signal with no dc content. The transmitter is a 6-tap (FIR) pre-emphasis equalizer with variable tap spacing. In simulation, the transmitter and receiver simultaneously communicate error-free at 8 Gb/s over the ac channel and at 500 Mb/s over the dc channel. Measurements shows that the ac and dc signals can be individually recovered and that the two signals occupy distinct frequency bands. View full abstract»

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  • Advanced Modeling and Accurate Characterization of a 16 Gb/s Memory Interface

    Publication Year: 2009 , Page(s): 306 - 327
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5053 KB) |  | HTML iconHTML  

    As the input/output (I/O) data rate increases to several gigabits per second, determining the performance of high-speed interfaces using conventional simulation and measurement techniques is becoming very challenging. The models of the interconnects have to be broadband and accurate to represent high frequency and second-order effects such as frequency dependence of dielectric losses and surface roughness. The large and small signal behaviors of the transmitter and receiver circuitries have to be correctly represented in link analysis. In addition, the system simulation needs to properly capture the interactions between the circuits and interconnect subsystems to optimize the overall system. However, determining the values of the critical link parameters and their correlations can be complicated. Some of the key parameters are not deterministic and some cannot be observed directly. A combined modeling and measurement approach is indispensable to determine the performance of high-speed links. This paper presents the modeling and characterization techniques employed in the design and verification of a 16 Gb/s bidirectional asymmetrical memory interface. Direct frequency and time-domain methods as well as indirect techniques based on bit-error-rate testing are used to model and determine important link parameters. Complex de-embedding procedures are utilized to extract parameters from externally observed data. On-chip measurements are also used to complement off-chip instrumentation and accurately measure the true performance of the link. The modeling and characterization of prototypes are also discussed and model-to-hardware correlations are presented at component and system levels. Based on both simulation and measurement results, the behavioral model of the complete system is constructed and statistical simulation technique is used to predict the yield and performance at low bit error rate. View full abstract»

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  • Is 25 Gb/s On-Board Signaling Viable?

    Publication Year: 2009 , Page(s): 328 - 344
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4220 KB) |  | HTML iconHTML  

    What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects. View full abstract»

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  • 160 Gb/s Bidirectional Polymer-Waveguide Board-Level Optical Interconnects Using CMOS-Based Transceivers

    Publication Year: 2009 , Page(s): 345 - 359
    Cited by:  Papers (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2164 KB) |  | HTML iconHTML  

    We have developed parallel optical interconnect technologies designed to support terabit/s-class chip-to-chip data transfer through polymer waveguides integrated in printed circuit boards (PCBs). The board-level links represent a highly integrated packaging approach based on a novel parallel optical module, or Optomodule, with 16 transmitter and 16 receiver channels. Optomodules with 16 Tx+16 Rx channels have been assembled and fully characterized, with transmitters operating at data rates up to 20 Gb/s for a 27-1 PRBS pattern. Receivers characterized as fiber-coupled 16-channel transmitter-to-receiver links operated error-free up to 15 Gb/s, providing a 240 Gb/s aggregate bidirectional data rate. The low-profile Optomodule is directly surface mounted to a circuit board using convention ball grid array (BGA) solder process. Optical coupling to a dense array of polymer waveguides fabricated on the PCB is facilitated by turning mirrors and lens arrays integrated into the optical PCB. A complete optical link between two Optomodules interconnected through 32 polymer waveguides has been demonstrated with each unidirectional link operating at 10 Gb/s achieving a 160 Gb/s bidirectional data rate. The full module-to-module link provides the fastest, widest, and most integrated multimode optical bus demonstrated to date. View full abstract»

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  • Foreword Wafer-Level Packaging: Interconnects for Enhanced Reliability

    Publication Year: 2009 , Page(s): 360 - 361
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    Freely Available from IEEE
  • Design, Fabrication, and Characterization of Novel Vertical Coaxial Transitions for Flip-Chip Interconnects

    Publication Year: 2009 , Page(s): 362 - 371
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3333 KB) |  | HTML iconHTML  

    In this paper, a novel transition design using vertical ldquocoaxial transitionrdquo for coplanar waveguide (CPW-to-CPW) flip-chip interconnect is proposed and presented for the first time. The signal continuity is greatly improved since the coaxial-type transition provides more return current paths compared to the conventional transition in the flip-chip structure. The proposed coaxial transition structure shows a real coaxial property from the 3-D electromagnetic wave simulation results. The design rules for the coaxial transition are presented in detail with the key parameters of the coaxial transition structure discussed. For demonstration, the back-to-back flip-chip interconnect structures with the vertical coaxial transitions have been successfully fabricated and characterized. The demonstrated interconnect structure using the coaxial transition exhibits the return loss below 25 dB and the insertion loss within 0.4 dB from dc to 40 GHz. Furthermore, the measurement and simulation results show good agreement. The novel coaxial transition demonstrates excellent interconnect performance for flip-chip interconnects and shows great potential for flip-chip packaging applications at millimeter waves. View full abstract»

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  • Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

    Publication Year: 2009 , Page(s): 372 - 378
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2158 KB) |  | HTML iconHTML  

    Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure. View full abstract»

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  • Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

    Publication Year: 2009 , Page(s): 379 - 389
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2828 KB) |  | HTML iconHTML  

    In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a J-shaped spring design produces a combination of high 3D compliances and acceptable electrical parasitics. Further, numerical analyses on the J -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 mum). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to ~35 GHz without significant power loss. View full abstract»

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  • Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging

    Publication Year: 2009 , Page(s): 390 - 398
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1503 KB) |  | HTML iconHTML  

    In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand the chip area and also to provide a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. The design concepts as well as the fabrication processes for the fan-out type FWLP would be described herein. In our previous research, it was shown the reliability of FWLP could easily pass 1300 cycles thermal cycling test (JEDEC condition G, -40degC ~ 125degC). Besides, the failure mode was moved from solders to copper trace lines. Therefore, the packaging level reliability of the copper trace structure of FWLP is investigated and discussed in this research. The 25 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging. Through the reliability assessment and constrained optimization technology, the fan-out FWLP could be further improved within the target range of design parameters. The FWLP structure proposed in this research can be redesigned to have the double-sided I/O capability, and will have a high potential for various advanced packaging applications. View full abstract»

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  • Foreword Special Section on Packaging for Micro/Nano-Scale Systems

    Publication Year: 2009 , Page(s): 399 - 401
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | PDF file iconPDF (678 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Performance Evaluation and Equivalent Model of Silicon Interconnects for Fully-Encapsulated RF MEMS Devices

    Publication Year: 2009 , Page(s): 402 - 409
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1543 KB) |  | HTML iconHTML  

    This paper aims to demonstrate the utility of silicon interconnects for radio-frequency (RF) microelectromechanical system (MEMS) devices that are packaged using a wafer-scale encapsulation process. Design and fabrication steps for the packaged interconnects are described. Measurement results show that encapsulated devices can be operated at frequencies up to 6 GHz with less than 1 dB insertion loss from the through-package silicon interconnects. This paper also describes a simple and accurate lumped-element model for simulating the performance of packaged silicon interconnects. The model is verified with S-parameter measurements from 50 MHz to 6 GHz. The modeling method and extracted values are intended to aid in the design and simulation of RF MEMS devices packaged using this technology. View full abstract»

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  • A Microfluidic Packaging Technique for Lab-on-Chip Applications

    Publication Year: 2009 , Page(s): 410 - 416
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1710 KB) |  | HTML iconHTML  

    In this paper, we address the often-neglected challenges of microfluidic packaging for biochemical sensors by proposing an efficient direct-write microfluidic packaging procedure. This low-cost procedure is performed through a programmable dispensing system right after a routine electronic packaging process. In order to prove the concept, the simulation, fabrication and chemical testing results of implemented hybrid system incorporating microelectronics and microfluidics are also presented and discussed. View full abstract»

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  • Design, Fabrication, and Assembly of an Optical Biosensor Probe Package for OCT (Optical Coherence Tomography) Application

    Publication Year: 2009 , Page(s): 417 - 422
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2074 KB) |  | HTML iconHTML  

    A miniaturized optical bioprobe package is developed using a 3-D micromirror and is tested for bio-imaging application. A silicon optical bench is designed and micromachined to assemble the fiber, lens, and the 3-D micromirror device. A 45deg angle trench is used to place the micromirror to achieve larger scanning range. Trace lines are formed on the optical bench and are connected to silicon micromirror using solder. A GRIN lens with lower numerical aperture has been used to focus the optical beam onto the micromirror. The bioprobe is packaged and is tested in a time domain optical coherence tomography (OCT) setup and optical image is obtained for plant tissue. View full abstract»

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  • Optimized Thermoelectric Refrigeration in the Presence of Thermal Boundary Resistance

    Publication Year: 2009 , Page(s): 423 - 430
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1297 KB) |  | HTML iconHTML  

    Thermoelectric refrigerators (TEMs) offer several advantages over vapor-compression refrigerators. They are free of moving parts, acoustically silent, reliable, and lightweight. Their low efficiency and peak heat flux capabilities have precluded their use in more widespread applications. Optimization of thermoelectric pellet geometry can help, but past work in this area has neglected the impact of thermal and electrical contact resistances. The present work extends a previous 1-D TEM model to account for a thermal boundary resistance and is appropriate for the common situation where an air-cooled heat sink is attached to a TEM. The model also accounts for the impact of electrical contact resistance at the TEM interconnects. The pellet geometry is optimized with the target of either maximum performance or efficiency for an arbitrary value of thermal boundary resistance for varying values of the temperature difference across the unit, the pellet Seebeck coefficient, and the contact resistances. The model predicts that when the thermal contact conductance is decreased by a factor of ten, the peak heat removal capability is reduced by at least 10%. Furthermore, when the interconnect electrical resistance rises above a factor of ten larger than the pellet electrical resistance, the maximum heat removal capability for a given pellet height is reduced by at least 20% and the maximum coefficient of performance at low Ku-infin,u/(NK) values is reduced by at least 50%. View full abstract»

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  • A Modular Stackable Concept for Heat Removal From 3-D Stacked Chip Electronics by Interleaved Solid Spreaders and Synthetic Jets

    Publication Year: 2009 , Page(s): 431 - 439
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (926 KB) |  | HTML iconHTML  

    A design for cooling 3-D stacked chip electronics is proposed using solid heat spreaders of high thermal conductivity interleaved between the chip layers. The spreaders conduct heat to the base of an advanced synthetic jet cooled heat sink. The stack conduction was investigated parametrically through computational modeling. The effect of the power dissipated, the heat transfer coefficient applied to the peripheral surface, the spreader thickness, spreader thermal conductivity, and the shape of via holes in the spreader were modeled. Results show that for moderate power dissipations, 5 W in each 27times38 mm layer, a 250 mum thick copper heat spreader would conduct heat adequately. In order to remove the heat from the edges of a five-layer stack and transfer it to the ambient air, a novel active heat sink design has been implemented using a matrix of integrated synthetic jets. In previous synthetic jet heat sink designs, cooling air is entrained upstream of the heat sink and is driven along the length of the fins, resulting in a significant rise in the air temperature and corresponding drop in streamwise heat transfer effectiveness. In the new design, synthetic jets emanate from the base of the fins so that the induced jets, and more importantly the entrained (cooling) ambient air, flow along the fin height. The significantly shorter flow path ensures rapid purging and replacement of the heated air with cool entrained air. Furthermore, in the matrix design the jets are spread uniformly throughout the heat sink such that all fin surfaces are subjected to the same airflow. The velocity field of the active heat sink is mapped using particle image velocimetry (PIV) and the configuration that maximizes the volume flow rate through the fins is investigated. Thermal performance is characterized using a surrogate heater and embedded thermocouple sensors. The thermal performance of identical heat sinks cooled by the two synthetic jet approaches is compared. View full abstract»

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  • Quantitative Characterization of True Leak Rate of Micro to Nanoliter Packages Using Helium Mass Spectrometer

    Publication Year: 2009 , Page(s): 440 - 447
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1222 KB) |  | HTML iconHTML  

    We propose a method to quantify the true leak rate of micro to nano-liter packages using the helium mass spectrometer. A new concept called ldquopreprocessing timerdquo is introduced to take into account 1) the instability of the helium mass spectrometer during the initial part of its operation and 2) the contribution of viscous conduction to the total conduction. The proposed method utilizes the complete profile of the apparent leak rate measured by the mass spectrometer and determines the true leak rate by performing a nonlinear regression analysis. The method is implemented successfully to measure the true leak rate of micro-electro-mechanical system packages. The validity of the proposed scheme is corroborated experimentally. View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering