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IEEE Transactions on Computers

Issue 7 • Date July 2009

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2009, Page(s): c2
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  • Process-Variation-Aware Adaptive Cache Architecture and Management

    Publication Year: 2009, Page(s):865 - 877
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3583 KB) | HTML iconHTML

    Fabricating circuits that employ ever-smaller transistors leads to dramatic variations in critical process parameters. This in turn results in large variations in execution/access latencies of different hardware components. This situation is even more severe for memory components due to minimum-sized transistors used in their design. Current design methodologies that are tuned for the worst case s... View full abstract»

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  • Efficient Software-Based Encoding and Decoding of BCH Codes

    Publication Year: 2009, Page(s):878 - 889
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3783 KB) | HTML iconHTML

    Error correction software for Bose-Chaudhuri-Hochquenghem (BCH) codes is optimized for general purpose processors that do not equip hardware for Galois field arithmetic. The developed software applies parallelization with a table lookup method to reduce the number of iterations, and maximum parallelization under a cache size limitation is sought for a high throughput implementation. Since this met... View full abstract»

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  • A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency

    Publication Year: 2009, Page(s):890 - 901
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2668 KB) | HTML iconHTML

    This paper presents the algorithm and implementation of a new high-performance functional unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is most frequently performed in 3D graphics application. The proposed IEEE-compliant DP4 unit computes Z = AB + CD + EF + GH in one path and keeps the intermediate rounding by IEEE-754 rounding to nearest even. The inte... View full abstract»

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  • Decimal Floating-Point Multiplication

    Publication Year: 2009, Page(s):902 - 916
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4274 KB) | HTML iconHTML

    Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry-save addition and one that employs binary carry-save addition. The multiplier based ... View full abstract»

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  • High-Performance Hardware Architectures for Galois Counter Mode

    Publication Year: 2009, Page(s):917 - 930
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6727 KB) | HTML iconHTML

    Various high-performance hardware architectures for Galois counter mode (GCM) in conjunction with various advanced encryption standard (AES) circuits and multiplier-adders are proposed. A total of 17 GCM-AES circuits were synthesized by using a 130-nm CMOS standard cell library, and the trade-offs between speed and hardware resources were evaluated. Our flexible architectures achieved a wide varie... View full abstract»

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  • A Process Algebraic View of Latency-Insensitive Systems

    Publication Year: 2009, Page(s):931 - 944
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1330 KB) | HTML iconHTML

    Latency-insensitive (LI) systems are those which can function correctly in spite of delays along its connecting wires. This delay is assumed to be a multiple of the clock period. The paper presents a single-clock process algebraic model for such systems. It gives the definitions for LI computational blocks and LI connectors. Important properties for these are shown to be satisfied. Composition of ... View full abstract»

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  • A Homogeneous Architecture for Power Policy Integration in Operating Systems

    Publication Year: 2009, Page(s):945 - 955
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2794 KB) | HTML iconHTML

    A significant volume of research has concentrated on operating system (OS)-directed power management. The primary focus of previous research has been the development of better policies. In this paper, we provide evidence that one policy may outperform another under different conditions. Hence, it is difficult, or even impossible, to design the "best" policy for all computers. We explain how to sel... View full abstract»

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  • Frame-Based Packet-Mode Scheduling for Input-Queued Switches

    Publication Year: 2009, Page(s):956 - 969
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2665 KB) | HTML iconHTML

    Most packet scheduling algorithms for input-queued switches operate on fixed-sized packets known as cells. In reality, communication traffic in many systems such as Internet runs on variable-sized packets. Motivated by potential savings of segmentation and reassembly, there has been increasing interest in scheduling variable-sized packets in a nonpreemptive manner known as packet-mode scheduling. ... View full abstract»

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  • Collusive Piracy Prevention in P2P Content Delivery Networks

    Publication Year: 2009, Page(s):970 - 983
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3218 KB) | HTML iconHTML

    Collusive piracy is the main source of intellectual property violations within the boundary of a P2P network. Paid clients (colluders) may illegally share copyrighted content files with unpaid clients (pirates). Such online piracy has hindered the use of open P2P networks for commercial content delivery. We propose a proactive content poisoning scheme to stop colluders and pirates from alleged cop... View full abstract»

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  • Hardware Architecture for High-Performance Regular Expression Matching

    Publication Year: 2009, Page(s):984 - 993
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1657 KB) | HTML iconHTML

    This paper presents a bitmap-based hardware architecture for the Glushkov nondeterministic finite automaton (G-NFA), which recognizes a given regular expression. We show that the inductions of the functions needed to construct the G-NFA can be generalized to include other special symbols commonly used in extended regular expressions such as the POSIX 1003.2 format. Our proposed implementation can ... View full abstract»

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  • Accurate Floating-Point Product and Exponentiation

    Publication Year: 2009, Page(s):994 - 1000
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    Several different techniques and softwares intend to improve the accuracy of results computed in a fixed finite precision. Here, we focus on a method to improve the accuracy of the product of floating-point numbers. We show that the computed result is as accurate as if computed in twice the working precision. The algorithm is simple since it only requires addition, subtraction, and multiplication ... View full abstract»

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  • Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials

    Publication Year: 2009, Page(s):1001 - 1008
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (853 KB) | HTML iconHTML

    This work studies efficient bit-parallel multiplication in GF(2m) for irreducible pentanomials, based on the so-called shifted polynomial bases (SPBs). We derive a closed expression of the reduced SPB product for a class of polynomials xm + xk s + xk s-1+ hellip + xk-1 + 1, with ks - k1 les m+1/ 2. T... View full abstract»

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  • TC Information for authors

    Publication Year: 2009, Page(s): c3
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    Freely Available from IEEE
  • [Back cover]

    Publication Year: 2009, Page(s): c4
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org