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Electron Device Letters, IEEE

Issue 10 • Date Oct. 1992

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Displaying Results 1 - 16 of 16
  • Silicon-carbide high-voltage (400 V) Schottky barrier diodes

    Page(s): 501 - 503
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    The authors describe the fabrication and characteristics of the first high-voltage (400-V) silicon-carbide (6H-SiC) Schottky barrier diodes. Measurements of the forward I-V characteristics of these diodes demonstrate a low forward voltage drop of approximately 1.1 V at an on-state current density of 100 A/cm/sup 2/ for a temperature range of 25 to 200 degrees C. The reverse I-V characteristics of these devices exhibit a sharp breakdown, with breakdown voltages exceeding 400 V at 25 degrees C. In addition, these diodes are shown to have superior reverse recovery characteristics when compared with high-speed silicon P-i-N rectifiers.<> View full abstract»

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  • InP/In/sub 0.53/Ga/sub 0.47/As heterojunction bipolar transistors with a carbon-doped base grown by MOCVD

    Page(s): 504 - 506
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    InP/In/sub 0.53/Ga/sub 0.47/As heterojunction bipolar transistors (HBTs) utilizing a carbon-doped base have been demonstrated. The devices were grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) using carbon tetrachloride (CCl/sub 4/) as the p-type dopant source. These devices exhibit a DC common-emitter current gain of 50 and an emitter-base junction ideality factor of 1.29 in a structure for which no undoped spacer layer was employed at the emitter-base junction. These preliminary results suggest that C-doping of In/sub 0.53/Ga/sub 0.47/As may be a suitable alternative to Zn in MOCVD-grown InP/In/sub 0.53/Ga/sub 0.47/As HBTs.<> View full abstract»

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  • Ultrashallow junctions for ULSI using As/sub 2//sup +/ implantation and rapid thermal anneal

    Page(s): 507 - 509
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    Using As/sub 2//sup +/ ion implantation and rapid thermal anneal, 40-nm n/sup +/-p junctions are realized. The junction formed with p/sup -/ substrate shows very low leakage current (<0.5 nA/cm/sup 2/) up to 2-V reverse bias. The introduction of a heavily doped (10/sup 18/ cm/sup -3/ level) p region generates a significantly higher leakage current due to the onset of band-to-band tunneling. Using varied geometry devices with a given area, the major tunneling current is shown to be confined in the perimeter of the device, and a method to suppress this leakage is suggested.<> View full abstract»

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  • Near-ideal I-V characteristics of GaInP/GaAs heterojunction bipolar transistors

    Page(s): 510 - 512
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    GaInP/GaAs heterojunction bipolar transistors (HBTs) have been fabricated and these devices exhibit near-ideal I-V characteristics with very small magnitudes of the base-emitter junction space-charge recombination current. Measured current gains in both 6- mu m*6- mu m and 100- mu m*100- mu m devices remain constant for five decades of collector current and are greater than unity at ultrasmall current densities on the order of 1*10/sup -6/ A/cm/sup 2/. For the 6- mu m*6- mu m device, the current gain reaches a high value of 190 at higher current levels. These device characteristics are also compared to published data of an abrupt AlGaAs/GaAs HBT having a base layer with similar doping level and thickness.<> View full abstract»

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  • Time-dependent dielectric breakdown characteristics of N/sub 2/O oxide under dynamic stressing

    Page(s): 513 - 515
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    Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-AA) N/sub 2/O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N/sub 2/O oxide has significant improvement in t/sub BD/ (2*under-V/sub g/ unipolar stress, 20*under+V/sub g/ unipolar stress, and 10*under bipolar stress). The improvement of t/sub BD/ in N/sub 2/O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO/sub 2//Si interface.<> View full abstract»

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  • Silicon-on-insulator approach for power IC's integrating vertical DMOS and polycrystalline silicon CMOS thin-film transistors

    Page(s): 516 - 518
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    A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions.<> View full abstract»

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  • Improvement of charge trapping characteristics of N/sub 2/O-annealed and reoxidized N/sub 2/O-annealed thin oxides

    Page(s): 519 - 521
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    It is found that increasing N/sub 2/O annealing temperature and time monotonically reduces electron trapping in the resulting oxides. The improvement increases with oxide thickness. Reoxidation does not enhance but reduces the improvement. The behavior is different from and simpler to understand than that after NH/sub 3/ annealing, apparently due to the absence of deleterious hydrogen. Hole trapping and interface trap generation are also suppressed by N/sub 2/O annealing, though an optimum anneal condition may exist. Charge to breakdown exhibits modest improvement consistent with reduced electron trapping.<> View full abstract»

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  • Hot-carrier effects in fully depleted submicrometer NMOS/SIMOX as influenced by back interface degradation

    Page(s): 522 - 524
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    From a systematic study of the hot-carrier-induced degradation in fully depleted submicrometer NMOS/SIMOX as a function of front- and back-gate biases during stress, the authors found that the apparent changes of the front-channel transistor parameters, measured at grounded back gate, could be largely attributed to the virtual back-gate bias effect arising from the trapped charge in the buried oxide. The strong dependence of carrier injection at the back interface on the back-gate bias and its resulting effect on the front-channel transistor parameters are also presented.<> View full abstract»

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  • InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtained by selective wet gate recess

    Page(s): 525 - 527
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    Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H/sub 2/O/sub 2/ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0- mu m gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively.<> View full abstract»

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  • Batch fabrication and structure of integrated GaAs-Al/sub x/Ga/sub 1-x/As field-effect transistor-self-electro-optic effect devices (FET-SEED's)

    Page(s): 528 - 531
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    The authors have demonstrated a smart pixel prototype field-effect-transistor-self-electrooptic-effect-device (FET-SEED) integrated optoelectronic amplifier utilizing process technology suitable for flexible design and fabrication of high-yield optoelectronic circuits. A single MBE growth sequence provides for quantum-well modulators, photodiodes, doped channel MIS-like field-effect transistors (DMTs), and resistors. The device dimensions are controlled in a planar technology using ion implantation and selective plasma etching for isolation and contacting. Results demonstrate optical amplification in a fully integrated circuit. This technology will enable increased functionality by providing digital electronic processing between optical input and output.<> View full abstract»

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  • Low-conductance drain (LCD) design of InAlAs/InGaAs/InP HEMT's

    Page(s): 535 - 537
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    The concepts of the low-conductance drain (LCD) design approach for lattice-matched InAlAs/InGaAs/InP HEMTs are demonstrated for improved device performance. The tradeoff for LCD HEMT characteristics is a tapered current gain cutoff frequency f/sub t/ under high drain-to-source bias. This behavior is, in principle, due to the fact that the LCD approach increases the effective gate length of the HEMTs in exchange for reduced peak channel electric field. Two-dimensional PISCES simulation was used to optimize the improvements while simultaneously minimizing this undesirable effect for an LCD HEMT structure.<> View full abstract»

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  • Hot-carrier-induced degradation of gate dielectrics grown in nitrous oxide under accelerated aging

    Page(s): 538 - 540
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    Gate oxides grown with partial and complete oxidation in N/sub 2/O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g/sub m/ had a 15*improvement over control oxides not grown in a N/sub 2/O atmosphere. Further improvement in g/sub m/ degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO/sub 2/ interface, leading to lower interface state generation (ISG). Improvements were also observed in I/sub g/-V/sub g/ characteristics, indicating a reduction of trap sites both at the Si/SiO/sub 2/ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N/sub 2/O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N/sub 2/O oxides and is a subject for further study.<> View full abstract»

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  • Effects of impact ionization on I-V characteristics of GaAs n-i-n structures including hole trap

    Page(s): 541 - 543
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    Numerical simulations of GaAs n-i-n structures with Cr deep acceptors (hole trap) in the i-layer are performed by considering the impact ionization of carriers. At low voltages, I-V curves show sublinear or saturated features, because the voltage is entirely applied along the reverse-biased n-i junction. When the deep-acceptor density is low, a steep rise of current occurs due to trap filling, whereas when the deep-acceptor density becomes high, the steep current rise occurs due to impact ionization of carriers at the reverse-biased n-i junction. In this case, the voltage for current rise becomes lower as the acceptor density becomes higher.<> View full abstract»

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  • Series resistance effects in thin oxide capacitor evaluation

    Page(s): 544 - 546
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    The effects of undesired series resistance in thin oxide capacitors are studied. Thin dielectric reliability is usually evaluated by means of accelerated tests (ramped or constant voltage or current stress). It is shown that the breakdown electric field can be highly overestimated due to the series resistance associated with the test structure: the larger the resistance, the bigger the error. Moreover, breakdown detection criteria in automatic test routines become more critical. It is also demonstrated that a nonuniform stress is applied to the dielectric whenever the series resistance is position-dependent, as it usually is. Erroneous breakdown-related defect distributions could be inferred as a consequence of neglecting the series resistance effect. It is therefore suggested that workers pay much attention to the test structure layout definition in order to minimize these problems.<> View full abstract»

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  • Comments, with reply, on 'Schottky contact effects in the sidegating effect of GaAs devices'

    Page(s): 547 - 548
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    The commenter points out a discrepancy between the results in the above-titled paper (ibid., vol.13, p.149-51, 1992) and those of C.P. Lee et al. (ibid., vol. EDL-3, p.97-8, 1982). He emphasizes that trap-fill-limited (TFL) conduction and trap-impact ionization are important mechanisms causing high substrate leakage current and backgating effect of GaAs MESFETs. He suggests that the dependence of the backgating and leakage current threshold voltage V/sub BGT/ on the source-to-drain bias V/sub DS/ of the MESFET can be used to experimentally evaluate if the observed backgating effect and leakage current are caused by mechanisms related to n-i-n or Schottky-i-n structures. The authors, in reply, amplify on the commenter's remarks and explain the discrepancy.<> View full abstract»

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  • A new method of determination of the I-V characteristics of negative differential conductance devices

    Page(s): 532 - 534
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    A method for mapping the complete I-V characteristic of a negative differential conductance (NDC) device has been investigated. This method employs the measurable positive differential conductance (PDC) portions of the DC I-V curve together with the measured conductances at a fixed DC bias voltage in the PDC region with different RF signal levels using a standard semiconductor analyzer. The NDC regime of the I-V curve is numerically constructed from the measured conductances at a fixed DC bias voltage in the PDC region with different signal levels using a large-signal nonlinear-circuit analysis.<> View full abstract»

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