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IEEE Transactions on Computers

Issue 12 • Dec 1988

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Displaying Results 1 - 18 of 18
  • Pairwise reduction for the direct, parallel solution of sparse, unsymmetric sets of linear equations

    Publication Year: 1988, Page(s):1648 - 1654
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A paradigm for concurrent computing is explored in which a group of autonomous, asynchronous processes shares a common memory space and cooperates to solve a single problem. The processes synchronize with only a few others at a time; barrier synchronization is not permitted except at the beginning and end of the computation. The paradigm maps directly to a shared-memory multiprocessor with efficie... View full abstract»

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  • A randomized parallel backtracking algorithm

    Publication Year: 1988, Page(s):1665 - 1676
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    A technique for parallel backtracking using randomization is proposed. Its main advantage is that good speedups are possible with little or no interprocessor communication. The speedup obtainable is problem-dependent. In those cases where the problem size becomes very large, randomization is extremely successful achieving good speedups. The technique also ensures high reliability, flexibility, and... View full abstract»

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  • Iterative algorithms for solution of large sparse systems of linear equations on hypercubes

    Publication Year: 1988, Page(s):1554 - 1568
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1096 KB)

    Finite-element discretization produces linear equations in the form Ax=b, where A is large, sparse, and banded with proper ordering of the variables x. The solution of such equations on distributed-memory message-passing multiprocessors implementing the hypercube topology is addressed. Iterative algorithms based on the conjugate gradient method are developed for... View full abstract»

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  • Simulating essential pyramids

    Publication Year: 1988, Page(s):1642 - 1648
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    Pyramid computers, and more generally pyramid algorithms, for image processing have the advantage of providing regular structure with a base naturally identified with an input image and a logarithmic height that permits rapid reduction of information. It is shown that it is possible to simulate systematically the effect of having a separate, so-called `essential' pyramid over each object, greatly ... View full abstract»

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  • Concurrent access of priority queues

    Publication Year: 1988, Page(s):1657 - 1665
    Cited by:  Papers (39)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    Contention for the shared heap limits the obtainable speedup in parallel algorithms using this data structure as a priority queue. An approach that allows concurrent insertions and deletions on the heap in a shared-memory multiprocessor is presented. The scheme retains the strict priority ordering of the serial-access heap algorithms, i.e. a delete operation returns the best key of all keys that h... View full abstract»

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  • Commutativity-based concurrency control for abstract data types

    Publication Year: 1988, Page(s):1488 - 1505
    Cited by:  Papers (89)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1628 KB)

    Two novel concurrency algorithms for abstract data types are presented that ensure serializability of transactions. It is proved that both algorithms ensure a local atomicity property called dynamic atomicity. The algorithms are quite general, permitting operations to be both partial and nondeterministic. The results returned by operations can be used in determining conflicts, thus allowing higher... View full abstract»

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  • The formal specification and design of a distributed electronic funds-transfer system

    Publication Year: 1988, Page(s):1515 - 1528
    Cited by:  Papers (11)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB)

    The design of an electronic funds-transfer (EFT) system, using the UNITY parallel programming methodology, is presented. The process begins with a high-level specification that captures the essence of transaction processing in the system. In a series of refinement steps, this specification is transformed into one that leads directly to a program suitable for execution on the distributed architectu... View full abstract»

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  • A compiler that increases the fault tolerance of asynchronous protocols

    Publication Year: 1988, Page(s):1541 - 1553
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1256 KB)

    A compiler that increases the fault tolerance of certain asynchronous protocols is presented. Specifically, it transforms a source protocol that is resilient to crash faults into an object protocol that is resilient to Byzantine faults. The compiler simplifies the design of protocols for the Byzantine fault model because it allows the design process to be broken in two steps. The first step is to ... View full abstract»

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  • Circuit simulation on shared-memory multiprocessors

    Publication Year: 1988, Page(s):1634 - 1642
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB)

    Reports the parallelization on a shared-memory vector multiprocessor of the computationally intensive components of a circuit simulator-matrix assembly (including device model evaluation) and the unstructured sparse linear system solution. A theoretical model is used to predict the performance of the lock-synchronized parallel matrix assembly, and the results are compared to experimental measureme... View full abstract»

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  • Efficient parallel convex hull algorithms

    Publication Year: 1988, Page(s):1605 - 1618
    Cited by:  Papers (63)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1444 KB)

    Parallel algorithms are presented to identify (i.e. detect and enumerate) the extreme points of the convex hull of a set of planar points using a hypercube, pyramid, tree, mesh-of-trees, mesh with reconfigurable bus, exclusive-read-exclusive-write parallel random-access machine (EREW PRAM), and modified AKS network. It is shown that the problem of identifying the convex hull for a set of planar po... View full abstract»

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  • Reliable broadcast in hypercube multicomputers

    Publication Year: 1988, Page(s):1654 - 1657
    Cited by:  Papers (85)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A simple algorithm for broadcasting in a hypercube multicomputer containing faulty nodes/links is proposed. The algorithm delivers multiple copies of the broadcast message through disjoint paths to all the modes in the system. Its salient feature is that the delivery of the multiple copies is transparent to the processes receiving the message and does not require the processes to know the identity... View full abstract»

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  • A novel technique for efficient parallel implementation of a classical logic/fault simulation problem

    Publication Year: 1988, Page(s):1569 - 1577
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB)

    A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as t... View full abstract»

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  • Constructing two-writer atomic registers

    Publication Year: 1988, Page(s):1506 - 1514
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A two-writer, n-reader atomic memory register is constructed from two one-writer, (n+1)-reader atomic memory registers. There are no restrictions on the size of the constructed register. The simulation requires only a single extra bit per real register and can survive the failure of any set of readers and writers. A complete proof of correctness is given. Several obvious ways are... View full abstract»

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  • Space-efficient and fault-tolerant message routing in outerplanar networks

    Publication Year: 1988, Page(s):1529 - 1540
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1172 KB)

    The problem of designing space- and communication-efficient routing schemes for networks that experience faults is addressed. For any outerplanar network containing t faults, a succinct routing scheme is presented that uses O(αtn) space and communication to generate routings that are less than ((α+1)/(α-1))t times longer than optimal, where α>... View full abstract»

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  • A benchmark parallel sort for shared memory multiprocessors

    Publication Year: 1988, Page(s):1619 - 1626
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (866 KB)

    The first parallel sort algorithm for shared memory MIMD (multiple-instruction-multiple-data-stream) multiprocessors that has a theoretical and measured speedup near linear is exhibited. It is based on a novel asynchronous parallel merge that evenly partitions data to be merged among any number of processors. A benchmark sorting algorithm is proposed that uses this merge to remove the linear time ... View full abstract»

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  • Synthesizing linear array algorithms from nested FOR loop algorithms

    Publication Year: 1988, Page(s):1578 - 1598
    Cited by:  Papers (59)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1676 KB)

    The mapping of algorithms structured as depth-p nested FOR loops into special-purpose systolic VLSI linear arrays is addressed. The mappings are done by using linear functions to transform the original sequential algorithms into a form suitable for parallel execution on linear arrays. A feasible mapping is derived by identifying formal criteria to be satisfied by both the original sequent... View full abstract»

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  • Partitioning techniques for large-grained parallelism

    Publication Year: 1988, Page(s):1627 - 1634
    Cited by:  Papers (35)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A model is presented for parallel processing in loosely coupled multiprocessing environments, such as networks of computer workstations, that are amenable to large-grained parallelism. The model takes into account the overhead involved in data communication to and from a remote processor and can be used to partition a large class of computations optimally, consisting of computations that can be or... View full abstract»

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  • A linear algebraic model of algorithm-based fault tolerance

    Publication Year: 1988, Page(s):1599 - 1604
    Cited by:  Papers (68)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A linear algebraic interpretation is developed for previously proposed algorithm-based fault tolerance schemes. The concepts of distance, code space, and the definitions of detection and correction in the vector space Rn are explained. The number of errors that can be detected or corrected for a distance-(d+1) code is derived. It is shown why the correction scheme does... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org