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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 6 • June 2009

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Displaying Results 1 - 22 of 22
  • Table of contents

    Publication Year: 2009, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2009, Page(s): C2
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  • An Outlook on Design Technologies for Future Integrated Systems

    Publication Year: 2009, Page(s):777 - 790
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (715 KB) | HTML iconHTML

    The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world. This paper surveys design require... View full abstract»

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  • Analog Placement Based on Symmetry-Island Formulation

    Publication Year: 2009, Page(s):791 - 804
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1449 KB) | HTML iconHTML

    To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposi... View full abstract»

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  • A Transform-Parametric Approach to Boolean Matching

    Publication Year: 2009, Page(s):805 - 817
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    In this paper, we address the problem of P-equivalence Boolean matching. We outline a formal framework that unifies some of the spectral- and canonical-form-based approaches to the problem. As a first major contribution, we show how these approaches are particular cases of a single generic algorithm, parametric with respect to a given linear transformation of the input function. As a second major ... View full abstract»

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  • Gate Sizing for Cell-Library-Based Designs

    Publication Year: 2009, Page(s):818 - 825
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB) | HTML iconHTML

    With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shift, the problem of discrete gate sizing has received significantly less attention than its continuous counterpart. On the other hand, cell sizes of many realistic libraries are sparse, for example, geometrically spaced, wh... View full abstract»

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  • Modeling and Experimental Measurement of Active Substrate-Noise Suppression in Mixed-Signal 0.18-$muhbox{m}$ BiCMOS Technology

    Publication Year: 2009, Page(s):826 - 836
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1623 KB) | HTML iconHTML

    Simulation and experimental results are presented for an active-noise-suppression technique to reduce substrate crosstalk in mixed-signal IC technology. The method utilizes a 3-D distributed resistive-capacitive substrate model, along with a BiCMOS wideband differential noise suppression amplifier (NSA) designed in IBM's 0.18-mum 7WL BiCMOS technology. Simulation results for a GR-defined ldquoquie... View full abstract»

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  • Resistance Estimation for Lateral Power Arrays Through Accurate Netlist Generation

    Publication Year: 2009, Page(s):837 - 845
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB) | HTML iconHTML

    Estimation of resistance of power devices has become critical for improving the efficiency of on-chip power-management circuits. In this paper, we present an efficient technique for estimation of resistance of a large lateral power-array layout along with parasitics. We extract a resistive network for metalizations utilizing the finite-element method. The method primarily benefits in terms of comp... View full abstract»

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  • Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions

    Publication Year: 2009, Page(s):846 - 859
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2423 KB) | HTML iconHTML

    For the successful electrical design of system-in-package, this paper proposes an efficient method for extracting wideband resistance and inductance from a large number of 3-D interconnections. The proposed method uses the modal equivalent network from the electric field integral equation with cylindrical conduction-mode basis function, which reduces the matrix size for large 3-D interconnection p... View full abstract»

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  • Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits

    Publication Year: 2009, Page(s):860 - 873
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (905 KB) | HTML iconHTML

    Thermal analysis has long been essential for designing reliable high-performance cost-effective integrated circuits (ICs). Increasing power densities are making this problem more important. Characterizing the thermal profile of an IC quickly enough to allow feedback on the thermal effects of tentative design changes is a daunting problem, and its complexity is increasing. The move to nanometer-sca... View full abstract»

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  • Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation

    Publication Year: 2009, Page(s):874 - 887
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (978 KB) | HTML iconHTML

    In this paper, we present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic structures and both die-to-die and within-die (WID) process variations, and taking into account the spatial correlation due to WID variations. Our model uses a ldquorandom-gaterdquo concept to capture high-level characteristics of a candidate ch... View full abstract»

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  • Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips

    Publication Year: 2009, Page(s):888 - 900
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (417 KB) | HTML iconHTML

    This paper introduces techniques for power-efficient design of power-delivery network (PDN) in multiple voltage-island system-on-chip (SoC) designs. The first technique is targeted to SoC designs with static-voltage assignment, while the second technique is pertinent to SoC designs with dynamic-voltage scaling (DVS) capability. Conventionally, a single-level configuration of dc-dc converters, wher... View full abstract»

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  • Using Data Compression for Increasing Memory System Utilization

    Publication Year: 2009, Page(s):901 - 914
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1110 KB) | HTML iconHTML

    The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in the amount of data they manipulate. The memory bottleneck is even more important for multiprocessor-system-on-a-chip (MPSoC) architectures due to the high cost of off-chip memory... View full abstract»

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  • Testing Resistive Opens and Bridging Faults Through Pulse Propagation

    Publication Year: 2009, Page(s):915 - 925
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB) | HTML iconHTML

    This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings shoul... View full abstract»

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  • Topology Synthesis of Cascaded Crossbar Switches

    Publication Year: 2009, Page(s):926 - 930
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    Performance requirements of on-chip network increase as system-on-chips (SoCs) are becoming more and more complex. For high-performance applications, crossbar switch-based networks are replacing the traditional shared buses as the backbone networks in SoCs. In this paper, we tackle the topology design of on-chip networks with crossbar switches in a cascaded fashion. We also resolve the unacceptabl... View full abstract»

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  • IEEE Embedded Systems Letters

    Publication Year: 2009, Page(s): 931
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  • 2010 IEEE International Symposium on Circuits and Systems (ISCAS2010)

    Publication Year: 2009, Page(s): 932
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    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2009, Page(s): 933
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • Scitopia.org [advertisement]

    Publication Year: 2009, Page(s): 934
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2009, Page(s): 935
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2009, Page(s): 936
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2009, Page(s): C3
    Request permission for commercial reuse | PDF file iconPDF (27 KB)
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu