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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2009

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Displaying Results 1 - 25 of 31
  • Table of contents

    Page(s): C1 - C2
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • EDS Membership at Your Service!

    Page(s): 1165
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  • Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects

    Page(s): 1166 - 1176
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1133 KB) |  | HTML iconHTML  

    This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented. View full abstract»

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  • Density of States of a-InGaZnO From Temperature-Dependent Field-Effect Studies

    Page(s): 1177 - 1183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (779 KB) |  | HTML iconHTML  

    Temperature-dependent field-effect measurements were performed on radio-frequency sputtered amorphous In-Ga-Zn-O thin film transistors (TFTs). We studied the effect of temperature on the TFT electrical properties. We observed that the field-effect mobility (mu) increases and the threshold voltage (V T) shifts negatively with temperature, while the current on-off ratio and subthreshold slope (S) remain almost unchanged. We also observed that the TFT drain current (ID) is thermally activated, and the relation between the prefactor (ID0) and activation energy (E a) obeys the Meyer-Neldel rule. The density of localized gap states (DOS) was then calculated by using a self-consistent method based on the experimentally obtained E a. The result shows good agreement with the DOS distribution calculated from SPICE simulations. View full abstract»

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  • Implementation of Electron–Phonon Scattering in a CNTFET Compact Model

    Page(s): 1184 - 1190
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB) |  | HTML iconHTML  

    This paper presents an extension of a ballistic compact model to the case of nonballistic transport for the conventional carbon nanotube FET featuring a MOSFET-like operation. A large part of the novelty lies on the analytical implementation of acoustic phonon (AP) and optical phonon (OP) scattering mechanism. To carry out this implementation, some simplifications of the theoretical description are proposed while staying as close as possible to physics and keeping the high-speed simulation and good convergence capability of the compact model. The compact model simulation results are systematically compared and validated with respect to nonequilibrium Green function simulation results. Then, we have investigated the impact of AP and OP scattering on transistor figures of merit. Taking into account the scattering processes is of utmost importance for both analog and digital circuit designs, since neglecting the scattering leads to an overestimation of more than 70% of the main figures of merit and will mislead designers when optimizing the operating point for analog applications. View full abstract»

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  • Full Quantum Treatment of Remote Coulomb Scattering in Silicon Nanowire FETs

    Page(s): 1191 - 1198
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (785 KB) |  | HTML iconHTML  

    We study the influence of remote Coulomb scattering (RCS) due to trapped charges at the silicon oxide/high- kappa material interface on the electrical performances of silicon nanowire (Si-NW) FETs. We address a full quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrdinger equation within the coupled mode-space non-equilibrium Green's function (NEGF) formalism. We find that the RCS strongly affects the electrical performances of Si-NWs by increasing both the inverse subthreshold voltage slope and the I off current. RCS-limited mobility, which is mainly determined by screening effects, is found to have quasi-linear dependence on the 1-D channel electron density, and its dependence on fixed charge density and interface layer thickness is discussed. View full abstract»

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  • Performance Evaluation of GaAs–GaP Core–Shell-Nanowire Field-Effect Transistors

    Page(s): 1199 - 1203
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (649 KB) |  | HTML iconHTML  

    We evaluate the performance of GaAs-GaP core-shell (C-S)-nanowire (NW) field-effect transistors by employing a semiclassical ballistic transport model. The valence-band structures of GaAs-GaP C-S NWs are calculated by using a kldrp method including the strain effect. The calculations show that the strain causes substantial band warping and pushes valence subbands to move up. We demonstrate that the on current can be enhanced with the strength of strain induced in the core, but an extremely thin equivalent oxide thickness may suppress the effect of the strain-induced current improvement. The achieved results can provide a design guide for optimizing device performance. View full abstract»

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  • The Effect of IEC-Like Fast Transients on RC -Triggered ESD Power Clamps

    Page(s): 1204 - 1210
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1035 KB) |  | HTML iconHTML  

    Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-mum CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a ldquolatch-onrdquo state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness. View full abstract»

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  • Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

    Page(s): 1211 - 1219
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    The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-V gs region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell. View full abstract»

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  • Platinum Germanosilicide Contacts Formed on Strained and Relaxed \hbox {Si}_{1 - x}\hbox {Ge}_{x} Layers

    Page(s): 1220 - 1227
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    Contact resistivity is a key contributor to the parasitic series resistance of nanoscale MOSFETs. Since the contact resistivity is an exponential function of the Schottky barrier height, new contact materials that can provide smaller barrier heights to source-drain junctions are needed. Platinum germanosilicide (PtSi1-xGex) is of interest as a contact material to the recessed Si1-xGex junctions of p-channel MOSFETs due to the large work function of platinum silicide (PtSi). In this paper, we explore the impact of in-plane biaxial compressive strain in Si1-xGex layers on PtSi1-xGex formation and the impact of the PtSi1-xGex on the strain in Si1-xGex. The parameters considered in this paper include the Ge content, the thickness of the Si1-xGex epitaxial layer, and the PtSi1-xGex thickness. The results show that the resistance, surface morphology, and the crystalline structure of the PtSi1-xGex films are independent of the strain in the original Si1-xGex layer. The results also indicate that PtSi1-xGex does not influence the strain in the Si1-xGex layer. The barrier-height measurements suggest the presence of Fermi-level pinning, and the pinning position is independent of the strain in the alloy, and it is primarily determined by the Ge concentration. As a result of Fermi-level pinning, hole Schottky barrier height of PtSi1-xGex-Si1-xGex contacts is 0.1-0.2 eV higher than that of the PtSi-Si contacts. View full abstract»

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  • A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

    Page(s): 1228 - 1234
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1333 KB) |  | HTML iconHTML  

    This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node. View full abstract»

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  • Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

    Page(s): 1235 - 1242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1240 KB) |  | HTML iconHTML  

    The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope (gm/SS) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I-V, as well as programming and erasing characteristics, and these must be taken into account in memory circuit design. View full abstract»

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  • Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

    Page(s): 1243 - 1251
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1442 KB) |  | HTML iconHTML  

    Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow IOFF (16 pA/mum) and high ION (N: 2.27 mA/mum and P: 1.32 mA/mum) currents are obtained on silicon on insulator (SOI) with a high-kappa/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-kappa/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher VDsat for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity. View full abstract»

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  • Multi-Channel Field-Effect Transistor (MCFET)—Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance

    Page(s): 1252 - 1261
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1495 KB) |  | HTML iconHTML  

    Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO2 and N+poly-Si/SiO2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position. View full abstract»

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  • Characterization of Inversion Tunneling Current Saturation Behavior for MOS(p) Capacitors With Ultrathin Oxides and High- k Dielectrics

    Page(s): 1262 - 1268
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    The inversion current conduction mechanism for MOS(p) capacitors with ultrathin oxides was analyzed from another aspect of bulk traps in this paper. The relationships between deep depletion and generation-recombination current were also studied. It was found that the generation-recombination current due to bulk traps is proportional to the deep-depletion width and dominates the inversion tunneling current. Moreover, it was observed that the inversion tunneling current levels for SiO2, Al2O3, and HfO2 gate dielectrics were different. This discrepancy was explained with their energy band diagrams. Due to the small conduction-band offset of HfO2, the gate dielectrics of HfO2 show a worse capability to block the inversion tunneling current in the saturation region than Al2O3 gate dielectrics. View full abstract»

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  • Pseudo-MOSFET Substrate Effects of Drain Current Hysteresis and Transient Behavior

    Page(s): 1269 - 1276
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (975 KB) |  | HTML iconHTML  

    A large drain current-gate voltage hysteresis of evaporated metal contact pseudo-MOSFETs ( Psi-MOSFET) is reported. The Psi-MOSFET drain current exhibits a hysteresis when the gate voltage is swept from negative to positive and from positive to negative voltages. Optical illumination, elevated temperatures, and decreased sweep rate during the measurements eliminate this phenomenon. The reason for this behavior is related to electron-hole pair generation in the substrate. In this paper, we report systematic studies and device simulations to document and understand these substrate effects during Psi-MOSFET measurements. View full abstract»

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  • Ultra High-Stress Liner Comprising Diamond-Like Carbon for Performance Enhancement of p-Channel Multiple-Gate Transistors

    Page(s): 1277 - 1283
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1101 KB) |  | HTML iconHTML  

    We report the demonstration of strained p-channel multiple-gate transistors or FinFETs with a novel liner-stressor material comprising diamond-like carbon (DLC). In this work, a DLC film with very high intrinsic compressive stress up to 6 GPa was employed. For FinFET devices having a 20 nm thin DLC liner stressor, more than 30% enhancement in saturation drain current IDsat is observed over FinFETs without a DLC liner. The performance enhancement is attributed to the coupling of compressive stress from the DLC liner to the channel, leading to hole mobility improvement. Due to its extremely high intrinsic stress value, significant IDsat enhancement is observed even when the thickness of the DLC film deposited is less than 40 nm. The DLC liner stressor is a promising stressor material for performance enhancement of p-channel transistors in future technology nodes. View full abstract»

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  • Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis

    Page(s): 1284 - 1291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (410 KB) |  | HTML iconHTML  

    The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure. View full abstract»

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  • Conductance Asymmetry of Graphene p-n Junction

    Page(s): 1292 - 1299
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (887 KB) |  | HTML iconHTML  

    We use the nonequilibrium Green function method in the ballistic limit to provide a quantitative description of the conductance of graphene p-n junctions - an important building block for graphene electronics devices. In this paper, recent experiments on graphene junctions are explained by a ballistic transport model, but only if the finite junction transition width D w is accounted for. In particular, the experimentally observed anomalous increase in the resistance asymmetry between n-n and n-p junctions under low source/drain charge density conditions is also quantitatively captured by our model. In light of the requirement for sharp junctions in applications such as electron focusing, we also examine the p-n junction conductance in the regime where D w is small and find that wave-function mismatch (so-called pseudospin) plays a major role in sharp p-n junctions. View full abstract»

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  • Compact Channel Noise Models for Deep-Submicron MOSFETs

    Page(s): 1300 - 1308
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    In this paper, compact channel noise models valid in all regions of operation for deep-submicron MOSFETs have been developed and experimentally verified. The physics-based expressions for thermal noise and flicker noise and corner frequency constitute compact channel noise models. The carrier heating, channel-length modulation, and mobility degradation due to the lateral electric field have been incorporated in the models. The effect of the mobility and carrier number fluctuations on the flicker noise, as well as the dependence of the mobility limited by Coulomb scattering on the inversion carrier density, have been considered in the flicker noise model. The measurement results validate the proposed models. View full abstract»

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  • Analysis of the Bipolar Current Mirror Including Electrothermal and Avalanche Effects

    Page(s): 1309 - 1321
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (673 KB) |  | HTML iconHTML  

    An experimental and numerical study of the bipolar current mirror characteristics under strong self-heating and avalanche conditions is presented, and a theoretical model to describe the observed behavior is proposed. It is shown that both electrothermal effects and impact ionization may lead to a marked degradation of the mirroring action, eventually resulting in an instability phenomenon which limits the usable operating range of the circuit. Both the separate and combined actions of these positive-feedback mechanisms are investigated. The model compares favorably with experimental data measured on silicon-on-glass and GaAs current mirrors and allows deriving a theoretical relation for the critical condition corresponding to the onset of the instability. The impact of the most significant technology and design parameters is discussed, and design criteria are given in order to ensure an unconditionally stable behavior. View full abstract»

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  • Pulsed I_{d} V_{g} Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling

    Page(s): 1322 - 1329
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    The pulsed current-voltage (I-V) measurement technique with pulse times ranging from ~17 ns to ~6 ms was employed to study the effect of fast transient charging on the threshold voltage shift DeltaV t of MOSFETs. The extracted DeltaV t values are found to be strongly dependent on the band bending of the dielectric stack defined by the high-kappa and interfacial layer dielectric constants and thicknesses, as well as applied voltages. Various hafnium-based gate stacks were found to exhibit a similar trap density profile. View full abstract»

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  • Interface-Engineered High-Mobility High- k /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness

    Page(s): 1330 - 1337
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1041 KB) |  | HTML iconHTML  

    High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO2 passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (Dit) of 2 times 1011 cm-2 ldr eV-1 for Ge MOS capacitors. A hole mobility up to 396 cm2/V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10-3 A/cm2 at Vt plusmn 1 V. A high drain current of 37.8 muA/mum at Vg - Vt = Vd = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times Dit reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors. View full abstract»

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  • A Simple Equivalent Circuit Analysis of the Dielectric Loss in a Helical Slow-Wave Structure of a Traveling-Wave Tube

    Page(s): 1338 - 1343
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    The electromagnetic field analysis of a helical slow-wave structure (SWS) is carried out based on a tape-helix model incorporating the effects of space-harmonic propagating modes and the surface current on the helix over the actual metallic area of the tape. Using this analysis, closed-form expressions are derived for the shunt capacitance per unit length and the shunt conductance per unit length of the transmission-line equivalent circuit of the structure. The analysis is interpreted for the circuit attenuation constant contributed by the loss of the dielectric helix-support rods. The analysis is accurate, amenable to easy computation, and validated against published results. The analysis is subsequently used for investigating the dielectric loss in an SWS due to the backward-wave (-1) space-harmonic mode of propagation. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology