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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 16 of 16

Publication Year: 2009, Page(s): C1
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2009, Page(s): C2
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• ### SEChecker: A Sequential Equivalence Checking Framework Based on ${K}$th Invariants

Publication Year: 2009, Page(s):733 - 746
Cited by:  Papers (1)  |  Patents (1)
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In recent years, considerable research efforts have been devoted to utilizing circuit structural information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in several efficient circuit-based SAT solvers. In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker. ... View full abstract»

• ### Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed–Solomon Codec

Publication Year: 2009, Page(s):747 - 757
Cited by:  Papers (25)
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In this paper, we present efficient algorithms for modular reduction to derive novel systolic and non-systolic architectures for polynomial basis finite field multipliers over GF(2m) to be used in Reed-Solomon (RS) codec. Using the proposed algorithm for unit degree reduction and optimization of implementation of the logic functions in the processing elements (PEs), we have derived a... View full abstract»

• ### Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM

Publication Year: 2009, Page(s):758 - 769
Cited by:  Papers (10)
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Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitiv... View full abstract»

• ### Clock Buffer Polarity Assignment for Power Noise Reduction

Publication Year: 2009, Page(s):770 - 780
Cited by:  Papers (4)
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Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive min-matching. A post-processing of cl... View full abstract»

• ### Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

Publication Year: 2009, Page(s):781 - 792
Cited by:  Papers (11)
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In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gat... View full abstract»

• ### Delta-Sigma Modulation for Direct Digital Frequency Synthesis

Publication Year: 2009, Page(s):793 - 802
Cited by:  Papers (6)
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This paper compares different DeltaSigma modulation techniques for direct digital frequency synthesis (DDS). DeltaSigma modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-mum CMOS technology with core area of 1.7times2.1 mm2 and total current consumption of 75 mA... View full abstract»

• ### Efficient EVM Testing of Wireless OFDM Transceivers Using Null Carriers

Publication Year: 2009, Page(s):803 - 814
Cited by:  Papers (8)
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High-volume manufacturing of current generation orthogonal frequency division multiplexing (OFDM) transceivers mandates testing for error-vector-magnitude (EVM) at production testing. During EVM test, a modulated RF input signal is down-converted and demodulated to obtain the output baseband digital data and EVM is computed by processing the baseband digital data. Hence, production testing of OFDM... View full abstract»

• ### Scan Chain Hold-Time Violations: Can They be Tolerated?

Publication Year: 2009, Page(s):815 - 826
Cited by:  Papers (2)  |  Patents (1)
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Scan chain hold-time violations may occur due to manufacturing defects or to errors in timing closure process during the physical design stage. The latter type of violations prohibits the test of manufactured chips, leading to a zero yield, although these chips with scan hold-time violations may be perfectly functional. In this paper, we propose a suite of techniques which enable the diagnosis and... View full abstract»

• ### A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment

Publication Year: 2009, Page(s):827 - 837
Cited by:  Papers (16)
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This paper presents a novel approach to reduce power in multimedia devices. Specifically, we focus on JPEG2000 as a case study. This paper indicates that by utilizing the in-built error resiliency of multimedia content, and the disjoint nature of the encoding and decoding processes, ultra low power architectures that are hardware fault tolerant can be conceived. These architectures utilize aggress... View full abstract»

• ### A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder

Publication Year: 2009, Page(s):838 - 843
Cited by:  Papers (14)  |  Patents (1)
| | PDF (1399 KB) | HTML

We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 times 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering res... View full abstract»

• ### A Timing-Dependent Power Estimation Framework Considering Coupling

Publication Year: 2009, Page(s):843 - 847
Cited by:  Papers (5)
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In this paper, a timing-dependent dynamic power estimation framework that considers the impact of coupling in combinational circuits is proposed. Relative switching activities and delays of coupled interconnects significantly affect dynamic power dissipation in parasitic coupling capacitances (coupling power). To enable capturing the switching and timing dependence, detailed switching distribution... View full abstract»

• ### Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping

Publication Year: 2009, Page(s):848 - 852
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Dynamic instruction scheduling logic is quite complex and dissipates significant energy in microprocessors that support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the complexity and energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required num... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2009, Page(s): C3
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

Publication Year: 2009, Page(s): C4
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu