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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 6 • Date June 2009

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Displaying Results 1 - 16 of 16
  • Table of contents

    Publication Year: 2009 , Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2009 , Page(s): C2
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  • SEChecker: A Sequential Equivalence Checking Framework Based on {K} th Invariants

    Publication Year: 2009 , Page(s): 733 - 746
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    In recent years, considerable research efforts have been devoted to utilizing circuit structural information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in several efficient circuit-based SAT solvers. In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker. We first introduce the notion of kth invariants. In contrast to the traditional invariants that hold for all cycles, k th invariants are guaranteed to hold only after the kth cycle from the initial state. We then present a bounded model checker (BMChecker) and an invariant checker (IChecker), both of which are based on circuit SAT techniques. Jointly, BMChecker and IChecker are used to compute the kth invariants, and are further integrated in a sequential circuit SAT solver for checking sequential equivalence. Experimental results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs that cannot be verified by existing solutions. View full abstract»

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  • Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed–Solomon Codec

    Publication Year: 2009 , Page(s): 747 - 757
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (601 KB) |  | HTML iconHTML  

    In this paper, we present efficient algorithms for modular reduction to derive novel systolic and non-systolic architectures for polynomial basis finite field multipliers over GF(2m) to be used in Reed-Solomon (RS) codec. Using the proposed algorithm for unit degree reduction and optimization of implementation of the logic functions in the processing elements (PEs), we have derived an efficient bit-parallel systolic design for finite field multiplier which involves nearly two-thirds of the area-complexity of the existing design having the same time-complexity. The proposed modular reduction algorithms are also used to derive efficient non-systolic serial/parallel designs of field multipliers over GF(28) with different digit-sizes, where the critical path and the hardware-complexity are further reduced by optimizing the implementation of modular reduction operations and finite field accumulations. The proposed bit-serial design involves nearly 55% of the minimum of area, and half the minimum of area-time complexity of the existing bit-serial designs. Similarly, the proposed digit-serial/parallel designs involve significantly less area, and less area-time complexities compared with the existing designs of the same digit-size. By parallel modular reduction through multiple degrees followed by appropriate logic-level sub-expression sharing; a hardware-efficient regular and modular form of a balanced-tree bit-parallel non-systolic multiplier is also derived. The proposed bit-parallel non-systolic pipelined design involves less than 65% of the area and nearly two-thirds of the area-time complexity of the existing bit-parallel design for a RS codec, while the non-pipelined form offers nearly 25% saving of area with less time-complexity. View full abstract»

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  • Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM

    Publication Year: 2009 , Page(s): 758 - 769
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1395 KB) |  | HTML iconHTML  

    Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitive (PI) technique is developed for via-programming ROM to reduce both fluctuations of peak current and cycle current across various input addresses and accessed code-patterns. The PI technique involves the arranging of the data patterns of a ROM-code and the adjustment of the structures of row decoders and peripheral circuits. Experiments based on the designed test-setup on fabricated 0.25 mum 256 kb ROM macros demonstrate the fluctuation in peak current of conventional ROM and its reduction by the PI technique. The fluctuations of measured peak and cycle currents of PI-ROM are only 0.7% and 13.1% of those of conventional ROM. The PI-ROM also has a 94.5% lower standby current than conventional ROM. View full abstract»

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  • Clock Buffer Polarity Assignment for Power Noise Reduction

    Publication Year: 2009 , Page(s): 770 - 780
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1070 KB) |  | HTML iconHTML  

    Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively. View full abstract»

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  • Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

    Publication Year: 2009 , Page(s): 781 - 792
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1042 KB) |  | HTML iconHTML  

    In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead about 1.76% on average, and an area overhead of 277%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the average delay overhead is about 3% and the average placed-and-routed area overhead is 28%, compared to an unprotected circuit (for delay mapped designs). We also propose an improved circuit protection algorithm to reduce the area overhead associated with our approach. With this approach for circuit protection, the area and delay overheads are further lowered. View full abstract»

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  • Delta-Sigma Modulation for Direct Digital Frequency Synthesis

    Publication Year: 2009 , Page(s): 793 - 802
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3300 KB) |  | HTML iconHTML  

    This paper compares different DeltaSigma modulation techniques for direct digital frequency synthesis (DDS). DeltaSigma modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-mum CMOS technology with core area of 1.7times2.1 mm2 and total current consumption of 75 mA. Measured DDS performance demonstrates that the frequency domain DeltaSigma modulation technique achieves better output spectrum purity than the phase domain method. Moreover, a programmable feedforward DeltaSigma modulator is proposed to achieve different in-band and out-band noise shaping effects for DDS applications. View full abstract»

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  • Efficient EVM Testing of Wireless OFDM Transceivers Using Null Carriers

    Publication Year: 2009 , Page(s): 803 - 814
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1618 KB) |  | HTML iconHTML  

    High-volume manufacturing of current generation orthogonal frequency division multiplexing (OFDM) transceivers mandates testing for error-vector-magnitude (EVM) at production testing. During EVM test, a modulated RF input signal is down-converted and demodulated to obtain the output baseband digital data and EVM is computed by processing the baseband digital data. Hence, production testing of OFDM devices would require such modulation- and demodulation-capable automated test equipment (ATE) to perform EVM test. Such capabilities significantly add up to the cost of the ATE, thereby increasing the overall cost of testing. Moreover, test time for EVM can be relatively long compared to other tests due to the need to average over a large number of data bits. In this paper, we propose a methodology for testing EVM using multi-tone signals sourced from inexpensive signal sources that generate standard constellations. Moreover, introducing null carriers in the multi-tone test stimulus enables accurate characterization of system noise with reduced number of data bits. This enables significant speedup in EVM testing. We present the theory to corroborate the proposed approach along with simulation and hardware results. The proposed test method also has the potential to significantly reduce EVM test time under production test conditions. View full abstract»

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  • Scan Chain Hold-Time Violations: Can They be Tolerated?

    Publication Year: 2009 , Page(s): 815 - 826
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (382 KB) |  | HTML iconHTML  

    Scan chain hold-time violations may occur due to manufacturing defects or to errors in timing closure process during the physical design stage. The latter type of violations prohibits the test of manufactured chips, leading to a zero yield, although these chips with scan hold-time violations may be perfectly functional. In this paper, we propose a suite of techniques which enable the diagnosis and the tolerance of scan hold-time violations. The proposed diagnosis technique can be utilized for any scan chain hold-time violation in order to pinpoint, in minimal diagnosis application time, the cause of the violation. The proposed tolerance technique is more targeted towards violations that lead to systematic failure of parts; it enables the generation of test patterns to screen out the defective parts in the presence of scan hold-time violations, perfectly restoring the yield in a cost-effective manner. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. We also extend this discussion for fast-to-rise and fast-to-fall errors, intermittent scan hold-time violations, and functional hold-time violations. View full abstract»

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  • A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment

    Publication Year: 2009 , Page(s): 827 - 837
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2080 KB) |  | HTML iconHTML  

    This paper presents a novel approach to reduce power in multimedia devices. Specifically, we focus on JPEG2000 as a case study. This paper indicates that by utilizing the in-built error resiliency of multimedia content, and the disjoint nature of the encoding and decoding processes, ultra low power architectures that are hardware fault tolerant can be conceived. These architectures utilize aggressive voltage scaling to conserve power at the encoder side while incurring extra processing requirements at the decoder to blindly detect and correct for encoder hardware induced errors. Simulations indicate a reduction of up to 35% in encoder power depending on the choice of technology for a 65-nm CMOS process. View full abstract»

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  • A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder

    Publication Year: 2009 , Page(s): 838 - 843
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1399 KB) |  | HTML iconHTML  

    We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 times 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering results every cycle. Taking advantage of skip modes, our filter takes only 48 cycles to filter a macroblock in the best case and 100 in the worst case. Furthermore, it eliminates most unnecessary off-chip memory traffic with a novel on-chip memory scheme. Our design can support QFHD at 30 fps application by running only at 98 MHz. View full abstract»

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  • A Timing-Dependent Power Estimation Framework Considering Coupling

    Publication Year: 2009 , Page(s): 843 - 847
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (446 KB) |  | HTML iconHTML  

    In this paper, a timing-dependent dynamic power estimation framework that considers the impact of coupling in combinational circuits is proposed. Relative switching activities and delays of coupled interconnects significantly affect dynamic power dissipation in parasitic coupling capacitances (coupling power). To enable capturing the switching and timing dependence, detailed switching distributions and timing information are essential in accurate estimation of dynamic power consumption. An approach to efficiently represent and propagate switching and timing distributions through circuits is developed. Based on propagated switching and timing distributions, power consumption in coupling capacitances is accurately calculated. Experimental results using ISCAS'85 benchmarks demonstrate that ignoring timing dependence of coupling power consumption can cause up to 25% error in dynamic power estimation (corresponding to 59% error in coupling power estimation). View full abstract»

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  • Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping

    Publication Year: 2009 , Page(s): 848 - 852
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    Dynamic instruction scheduling logic is quite complex and dissipates significant energy in microprocessors that support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the complexity and energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required number of ports and the size of the structure. This paper describes the microarchitecture mechanisms and shows evaluation results for energy savings and performance. These results reveal that the proposed technique can greatly reduce energy with almost no performance degradation, compared to the conventional dynamic instruction scheduling logic. View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2009 , Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2009 , Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu