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IEEE Transactions on Computers

Issue 1 • Date Jan. 1993

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Displaying Results 1 - 16 of 16
  • An angle recoding method for CORDIC algorithm implementation

    Publication Year: 1993, Page(s):99 - 102
    Cited by:  Papers (50)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB)

    The coordinate rotation digital computer (CORDIC), an iterative arithmetic algorithm for computing generalized vector rotations without performing multiplications, is discussed. For applications where the angle of rotation is known in advance, a method to speed up the execution of the CORDIC algorithm by reducing the total number of iterations is presented. This is accomplished by using a techniqu... View full abstract»

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  • Correction to 'Hard-wired multipliers with encoded partial products'

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (110 KB)

    Several typographical errors in the above-named work (see ibid., vol.40, no.11, p.1181-97 (1991)) are corrected.<> View full abstract»

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  • Performance tradeoffs in rings of data-driven elements

    Publication Year: 1993, Page(s):113 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A method for maintaining causality within medium grained cellular based architectures is discussed. The strategy combines the benefits of data-driven communication with a hardware simplicity, latency and throughput rate approaching that of globally checked systolic arrays. It is shown that with this strategy higher throughput rates and lower latencies can be achieved by using slower processing ele... View full abstract»

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  • A systematic (16,8) code for correcting double errors and detecting triple-adjacent errors

    Publication Year: 1993, Page(s):109 - 112
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A double error correcting systematic (16,8) quasi-cycle (QC) code that can detect all triple-adjacent errors within each 8-b byte is presented. This code is useful in computer memory applications where adjacent errors are more likely than random errors. As an alternative, a systematic (24,16) QC code is given which corrects single errors, and detects all double errors in addition to all triple-adj... View full abstract»

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  • Multiple-valued counter

    Publication Year: 1993, Page(s):106 - 109
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    The use of resonant tunneling diodes (RTDs) in multivalued counters, which greatly simplify the counter circuitry, is described. In order to achieve this implementation, a unique state-dependent current source is used to successively trigger RTD-based counter View full abstract»

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  • Some results on a SRT type division scheme

    Publication Year: 1993, Page(s):102 - 106
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A variation of a division method previously presented by the author (1990) is described. The method is of the SRT type. This present scheme is based upon a system of recursion equations derived from the equation 1/A=Q. Its advantages are presented View full abstract»

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  • Combinatorial analysis of the fault-diameter of the n-cube

    Publication Year: 1993, Page(s):27 - 33
    Cited by:  Papers (58)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    It is shown that the diameter of an n-dimensional hypercube can only increase by an additive constant of 1 when (n-1) faulty processors are present. Based on the concept of forbidden faulty sets, which guarantees the connectivity of the cube in the presence of up to (2n-3) faulty processors. It is shown that the diameter of the n-cube increases to (n-2)... View full abstract»

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  • OPSILA: a vector and parallel processor

    Publication Year: 1993, Page(s):76 - 82
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    A multiprocessor machine with two operating modes and simple synchronization mechanisms is discussed. The operating modes are the vector single-instruction multiple-data (SIMD) mode and the parallel single program stream, multiple data stream (SPMD) mode. Synchronizations are reduced to the switching between these two modes. Mixing these two operating modes offers the programmer a comfortable prog... View full abstract»

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  • An improved method for constructing multiphase communications protocols

    Publication Year: 1993, Page(s):15 - 26
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    An extension to an existing method for building multiphase protocols is presented. One of the limitations of the former method is a stringent restriction on the validity of phases. Consequently, the protocols built by this method must run in a noiseless environment or rely on other protocols for reliable transport. Another restriction is a rigid requirement on the selection of the points that conn... View full abstract»

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  • Dependability measurement and modeling of a multicomputer system

    Publication Year: 1993, Page(s):62 - 75
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1196 KB)

    A measurement-based analysis of error data collected from a DEC VAXcluster multicomputer system is presented. Basic system dependability characteristics such as error/failure distributions and hazard rate are obtained for both the individual machine and the entire VAXcluster. Markov reward models are developed to analyze error/failure behavior and to evaluate performance loss due to errors/failure... View full abstract»

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  • Computing functions cos-1 and sin-1 using CORDIC

    Publication Year: 1993, Page(s):118 - 122
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    An extension of the CORDIC (coordinate rotation digital computer) algorithm that makes it possible to compute the functions cos-1 , sin-1, √1-t2, sinh-1 cosh-1, and √1+t2 is presented. The algorithms are suitable for VLSI implementation and require only a slight modification of the original CORDIC algo... View full abstract»

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  • High-bandwidth interleaved memories for vector processors-a simulation study

    Publication Year: 1993, Page(s):34 - 44
    Cited by:  Papers (27)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    A family of alternate interleaving schemes called permutation-based interleaving schemes for improving memory bandwidth for a wide range of access patterns in high-performance vector processing systems is described. Permutation-based interleaving schemes can be implemented with a small amount of additional hardware and with a minimal time overhead. The results of a detailed simulation analysis are... View full abstract»

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  • Performance evaluation of a threshold policy for scheduling readers and writers

    Publication Year: 1993, Page(s):83 - 98
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1124 KB)

    An analysis of a threshold policy for scheduling readers and writers in a multiserver system and a comparison of its performance with the first-come, first-served (FCFS) policy are presented. The threshold fastest emptying (FTE) policy is analyzed in a system with writer arrivals and an infinite backlog of readers using a Markovian model as well as a vacationing server model to yield closed-form e... View full abstract»

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  • Modeling live and dead lines in cache memory systems

    Publication Year: 1993, Page(s):1 - 14
    Cited by:  Papers (12)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    An analytical model that predicts the fraction of live and dead lines present in a cache memory in a multitasking environment is presented. The model is two-fold. The first portion evaluates the number of live lines created in a fully associative cache during the execution of a process. The second portion models the interaction of two processes that share a cache and run in an interleaved fashion.... View full abstract»

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  • Interrupt handling for out-of-order execution processors

    Publication Year: 1993, Page(s):122 - 127
    Cited by:  Papers (11)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Processors with multiple functional units, including the superscalars, achieve significant performance enhancement through low-level execution concurrency. In such processors, multiple instructions are often issued and definitely executed concurrently and out-of-order. Consequently, interrupt and exception handling becomes a vexing problem. The authors identify latency, cost, and performance degra... View full abstract»

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  • Vertical migration of software functions and algorithms using enhanced microsequencing

    Publication Year: 1993, Page(s):45 - 61
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1308 KB)

    A scheme for vertical migration of algorithms and functions with complex sequencing structure from software through firmware into microcoded VLSI structures is discussed. The expected benefits of migration are gains in speed, reliability, and stability. The scheme employs a migration model that is based on microcode modularity and is supported by a hardware microcontroller with enhanced sequencing... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org