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Solid-State Circuits, IEEE Journal of

Issue 2 • Date Feb 1993

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Displaying Results 1 - 14 of 14
  • Comments on circuit models for MOSFET thermal noise

    Publication Year: 1993 , Page(s): 184 - 185
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    It is shown that some current and proposed SPICE models for MOS thermal noise are inconsistent, either when moving from one operating region to another or when changing model levels. A different model is shown to be consistent with theory in all regions and with all SPICE model levels. The reasons for the inconsistency are explored View full abstract»

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  • A generalized tanh law MOSFET model and its applications to CMOS inverters

    Publication Year: 1993 , Page(s): 176 - 179
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A generalized tanh law model is proposed to simulate the current-voltage characteristics of both long-channel and short-channel MOS transistors. The proposed model is used to calculate the propagation delay, short-circuit power dissipation, and logic threshold voltage of CMOS inverters. The results obtained are in good agreement with those obtained using classical models View full abstract»

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  • A clock feedthrough reduction circuit for switched-current systems

    Publication Year: 1993 , Page(s): 133 - 137
    Cited by:  Papers (37)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20% View full abstract»

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  • Layout reconstruction of complex silicon chips

    Publication Year: 1993 , Page(s): 138 - 145
    Cited by:  Papers (2)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    A semiautomated, fast-turnaround and high-reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices View full abstract»

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  • An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs

    Publication Year: 1993 , Page(s): 180 - 183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Short-channel effects on the subthreshold behavior are modeled in self-aligned gate AlGaAs/GaAs MODFETs through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of short-channel effects in enhancement-mode MODFETs with and without i-AlGaAs spacer layers indicates that channel lengths will be limited to 0.18-0.25 μm by subthreshold conduction. Minimum gate lengths for MODFETs with a spacer layer are notably larger than those without a spacer layer. Besides offering insights into the physics of short-channel effects in MODFETs, the model provides a useful basis for efficient design, analysis, and simulation of small geometry AlGaAs/GaAs MODFET digital circuits View full abstract»

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  • A 200 MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design

    Publication Year: 1993 , Page(s): 123 - 132
    Cited by:  Papers (33)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    A bit-level pipelined 12 b×12 b two's complement multiplier with a 27 b accumulator has been designed and fabricated in 1.0 μm p-well CMOS technology. A new quasi N-P domino logic structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10000 transistors and the die area is 2.5 mm×3.7 mm. The measured maximum clock rate is 200 MHz (i.e. 200 million multiply-accumulate operations per second), and the power-speed ratio is 6.5 mW/MHz. A unique output buffer design was also adopted to achieve 200 MHz off-chip communication while maintaining full CMOS logic levels View full abstract»

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  • Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

    Publication Year: 1993 , Page(s): 146 - 156
    Cited by:  Papers (30)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1116 KB)  

    A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method View full abstract»

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  • 20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems

    Publication Year: 1993 , Page(s): 115 - 122
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    Design principles for achieving good eye opening and circuit optimization to extract high performance from AlGaAs/GaAs heterojunction bipolar transistor (HBT) devices are described. Using the circuit techniques and HBTs with an fT of 70 GHz and an fmax of 50 GHz, four kinds of SSIs are developed for future optical transmission systems. High-bit-rate operation of over 20 Gb/s (26 GHz toggle flip-flop, 20 Gb/s decision circuit, 20 Gb/s EXCLUSIVE OR/NOR gate, and 28 Gb/s selector IC), extremely fast rise and fall times (20-80%) of 20 and 14 ps, respectively, and good eye opening are obtained. In addition, potential performance gains that might be realized through advanced circuit and device design are appraised, and throughputs as fast as 40 Gb/s are predicted View full abstract»

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  • An analytical threshold voltage and subthreshold current model for short-channel MESFETs

    Publication Year: 1993 , Page(s): 169 - 172
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits View full abstract»

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  • Novel area-time efficient static CMOS totally self-checking comparator

    Publication Year: 1993 , Page(s): 165 - 168
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    The comparator is an essential element in concurrent error detection (CED). To ensure the correctness of error detection processes, comparators must be totally self-checking (TSC): any single fault occurring in the comparator must be detected by at least one normal input pattern, and before the detection of that fault, no erroneous output must be guaranteed. An area-time efficient static CMOS TSC comparator design is presented. This comparator uses only eight transistors and is totally self-checking with respect to stuck-at, stuck-open, stuck-on, bridging faults, and breaks View full abstract»

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  • A new waveform-reshaping circuit: an alternative approach to Schmitt trigger

    Publication Year: 1993 , Page(s): 162 - 164
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    A waveform-reshaping circuit that is conceived as an alternative to the conventional Schmitt trigger is introduced. This circuit employs ratioless inverters, which require no standby current and are for high-speed operations. Two different logic threshold voltages of the CMOS inverters in the circuit determine the hysteresis characteristics View full abstract»

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  • Impedance boosting techniques based on BiCMOS technology

    Publication Year: 1993 , Page(s): 157 - 161
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    An impedance enhancement technique, based on a combination of bipolar and MOS devices, is presented. The technique uses negative active feedback action to boost the impedance level of a cascode circuit. This technique improves the gain of the conventional folded-cascode BiCMOS amplifier by the loop gain of the feedback loop. The BiCMOS-based impedance boosting circuit, compared to the CMOS version, offers the advantage of higher bandwidth together with higher output current capability. The SPICE simulations of a folded-cascode op amp based on this technique show that a 120 dB DC gain can be achieved. Application of the technique to a transducer resulted in a total harmonic distortion as low as 0.02% with 2 Vp-p input signals and an improvement of more than 10 dB in linearity, with respect to the case where no feedback was used View full abstract»

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  • A new model for bipolar transistors at high current

    Publication Year: 1993 , Page(s): 173 - 175
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    A model for current gain and cutoff frequency falloff at high currents for bipolar transistors is proposed. The model is based on considering that the vertical and lateral base widening occur simultaneously for a typical bipolar transistor. The results of this model successfully fit Pisces-2B simulation results View full abstract»

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  • A self-learning digital neural network using wafer-scale LSI

    Publication Year: 1993 , Page(s): 106 - 114
    Cited by:  Papers (18)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB)  

    A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 μm CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan