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Design & Test of Computers, IEEE

Issue 2 • Date March-April 2009

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  • [Front cover]

    Publication Year: 2009 , Page(s): c1
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  • [Front cover]

    Publication Year: 2009 , Page(s): c2
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  • Call for Papers

    Publication Year: 2009 , Page(s): 1
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  • Contents

    Publication Year: 2009 , Page(s): 2 - 3
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  • Managing design and test challenges

    Publication Year: 2009 , Page(s): 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB) |  | HTML iconHTML  

    Risks are notably increasing in the design of complex SoCs at the 65-nm technology node and beyond. Escalating design costs, increasing profitability and time-to-market pressures, and skyrocketing power consumption—in conjunction with a lower first-silicon success rate, and lower chip manufacturability and reliability—are among the key challenges that chip makers are confronting. To minimize the risks in the face of these challenges requires skillful management of the design process, which has become a core competency of leading chip makers. This issue of Design & Test features a special issue on the management of emerging SoC development. The special issue consists of four articles, contributed by experienced design managers from leading semiconductor companies. In addition, four general-interest articles address diverse design and test issues. View full abstract»

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  • [Masthead]

    Publication Year: 2009 , Page(s): 5
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  • Guest Editor's Introduction: Examples of Management Decision Criteria

    Publication Year: 2009 , Page(s): 6 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    Consumer application chips are the technology drivers today. Their design and test require different types of optimizations to address, on the one hand, the technology challenges, and on the other, very high volume production. This will necessitate adopting emerging solutions to meet such requirements. Optimizing for high-volume production, low power, and shrinking sizes necessitates adequate trade-off analysis, along with technical and business decision making by management. Also, moving to new semiconductor technology nodes, such as 45 nm and 32 nm, can significantly affect the choices of suppliers. This special issue discusses these requirements and demonstrates corresponding management decision criteria to make the right choices from a pool of alternate options for flows, methodologies, tools, and IP blocks. View full abstract»

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  • The Story behind the Intel Atom Processor Success

    Publication Year: 2009 , Page(s): 8 - 13
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1217 KB) |  | HTML iconHTML  

    Many state-of-the-art designs, besides their technical challenges, require robust project execution to meet their target. This article presents the Intel Atom processor as an example to analyze from its management perspective the effectiveness of project execution, including organizational structure and geographical distribution, timely decision making, milestone definition, tracking progress, and fast recovery from surprises. View full abstract»

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  • Case Study of a 65-nm SoC Design

    Publication Year: 2009 , Page(s): 14 - 19
    Cited by:  Papers (2)
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    IC design flow is increasing in complexity. Adopting new technologies and advanced IP blocks from multiple sources is not sufficient to solve the problem. Special management and system integration plans are necessary. This article describes a set of management and integration initiatives adopted by MediaTek to address this problem. View full abstract»

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  • Low-Power Design Solutions for Wireless Multimedia SoCs

    Publication Year: 2009 , Page(s): 20 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3881 KB) |  | HTML iconHTML  

    With advanced semiconductor technology nodes, power management has become a global problem. In battery powered applications, this problem is even more critical. This article describes a range of design solutions that STMicroelectronics uses to manage dynamic and static power while meeting its targets for area and performance. View full abstract»

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  • From Specification to High-Volume Production

    Publication Year: 2009 , Page(s): 30 - 33
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB) |  | HTML iconHTML  

    In order to meet the ever shrinking market window, the ability to ramp up chip volume production has become a significant challenge. This is due to simultaneous changes in technology, functionality, schedule, cost, etc. This article presents a set of requirements and a unique design flow developed by SanDisk to help meet on-time volume production. View full abstract»

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  • Incremental Verification with Error Detection, Diagnosis, and Visualization

    Publication Year: 2009 , Page(s): 34 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1254 KB) |  | HTML iconHTML  

    Invers is a fast incremental-verification system for physical-synthesis optimization that includes capabilities for error detection, diagnosis, and visualization. Using a new metric called the similarity factor, Invers can help engineers identify potential errors earlier in development. Invers employs traditional verification only when necessary to ensure completeness of the verification flow. It also provides an error visualization interface to simplify error isolation and correction. View full abstract»

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  • Computing and Minimizing Cache Vulnerability to Transient Errors

    Publication Year: 2009 , Page(s): 44 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB) |  | HTML iconHTML  

    Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance. View full abstract»

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  • Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

    Publication Year: 2009 , Page(s): 52 - 63
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1300 KB) |  | HTML iconHTML  

    Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches-one fully automated and one deterministically guided-and propose a novel combination of the two schemes that can be applied in a generic manner on a wide set of communication cores. View full abstract»

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  • Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

    Publication Year: 2009 , Page(s): 64 - 73
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1657 KB) |  | HTML iconHTML  

    Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics. View full abstract»

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  • DATC Newsletter

    Publication Year: 2009 , Page(s): 1 - 2
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  • Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews]

    Publication Year: 2009 , Page(s): 76 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    This is a review of Processor Description Languages (edited by Prabhat Mishra and Nikil Dutt). This book is likely to become the main resource for anyone wanting to understand the ADL area in detail. The book's 14 chapters contain detailed descriptions of 11 industrial and academic ADLs used for ASIP creation. In addition, it summarizes the salient features of eight more approaches in a concluding chapter. It thus can serve as the standard comparative reference work for this approach to processor-centric design for several years to come. View full abstract»

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  • TTTC Newsletter

    Publication Year: 2009 , Page(s): 1 - 2
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  • CEDA Currents

    Publication Year: 2009 , Page(s): 80 - 83
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  • Technical management: Best shaken, not stirred [The Last Byte]

    Publication Year: 2009 , Page(s): 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB) |  | HTML iconHTML  

    Compares creating and managing the perfect design team - and the perfect chip - to creating the perfect martini. View full abstract»

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  • Advertisement - CS Press

    Publication Year: 2009 , Page(s): c3
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  • [Avertisement]

    Publication Year: 2009 , Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty