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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 2 • Date April 2009

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Displaying Results 1 - 13 of 13
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Electronics Packaging Manufacturing publication information

    Page(s): C2
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  • Nonconductive Films (NCFs) With Multifunctional Epoxies and Silica Fillers for Reliable NCFs Flip Chip on Organic Boards (FCOBs)

    Page(s): 65 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4135 KB) |  | HTML iconHTML  

    Nonconductive films (NCFs) have become one of the promising interconnection adhesives for flip-chip assembly. Because NCFs have many advantages such as low cost, easy handling, and fine-pitch application. However, effects of the material properties of NCFs on the reliability of NCFs flip-chip assemblies have not been fully understood. In this paper, effects of multifunctional epoxy and the addition of silica fillers on thermomechanical properties of cured NCFs and thermal cycling reliability of NCFs flip-chip-on-organic board (FCOB) assemblies were investigated. For the NCF materials, two kinds of thermosetting polymers, di-functional and multifunctional epoxies, and silica fillers of various contents (0 wt%, 10 wt%, and 20 wt%) were used. The curing behavior and thermomechanical properties of NCFs were measured for the NCF materials characterization. According to the results, NCFs using multifunctional epoxy had higher glass transition temperature (Tg), lower coefficient of thermal expansion (CTE), and higher storage modulus (E') in high-temperature regions than NCFs using di-functional epoxy. As the silica filler content increased, the CTE and the storage modulus of cured NCFs decreased and increased, respectively. Thermal cycling test (-40degC - 150degC, 1000 cycles) was performed to investigate effects of thermomechanical properties of cured NCFs on thermal cycling reliability of NCF FCOB assemblies. According to the results, NCF FCOB assemblies using NCFs with multifunctional epoxy had better thermal cycling reliability than those using NCFs with di-functional epoxy, and 10 wt% and 20 wt% silica added NCFs showed the best thermal cycling reliability in the electroplated Au bump application and the stud Au bump application, respectively. Consequently, thermal cycling reliability of NCFs FCOB assemblies could be enhanced with the increased Tg and the improved thermomechanical properties of NCFs by using multifunctional epoxy and the addi- - tion of silica fillers. View full abstract»

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  • Effects of Anisotropic Conductive Film Viscosity on ACF Fillet Formation and Chip-On-Board Packages

    Page(s): 74 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2318 KB) |  | HTML iconHTML  

    In this paper, the effects of anisotropic conductive film (ACF) viscosity on ACF fillet formation and, ultimately, on the pressure cooker test (PCT) reliability of ACF flip chip assemblies were investigated. The ACF viscosity was controlled by varying the molecular weight of the epoxy materials. It was found that the ACF viscosity increased as the increase of molecular weight of the epoxy materials. However, there was little variation of the thermomechanical properties among the evaluated ACFs with different viscosites. Also, the results showed that the ACFs have no differences in moisture absorption rate, die adhesion strength, and degree-of-cure. In scanning electron microscopy images, the lower ACF viscosity resulted in the smoother ACF fillet shape and the higher fillet height. From the results of PCT, the ACF flip chip assembly with the smoother fillet shape showed better reliability in terms of contact resistance changes. After 130 h of PCT, the flip chip assembly with lower ACF viscosity also showed a lesser degree of delamination at the ACF/chip interface. View full abstract»

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  • Parameter Modeling for Wafer Probe Test

    Page(s): 81 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1703 KB) |  | HTML iconHTML  

    This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test. View full abstract»

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  • Modeling of Soldering Quality by Using Artificial Neural Networks

    Page(s): 89 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (497 KB) |  | HTML iconHTML  

    Multilayer perceptrons (MLPs ) are well-known artificial neural networks (ANNs) that are used in many different applications. In this paper, MLP neural networks were used to predict product quality in a wave soldering research case. The aims were to construct process models and to determine whether the formation of soldering defects could be predicted reliably by using the method. In addition, the scope of the research included demonstrating the prediction performance of the created models. A MLP-based variable selection procedure with a back-propagation algorithm was used to create defect formation models and to find the most important factors affecting the number of detected defects. The process parameters were used as inputs for the MLP network and each defect type in turn as a model output. In conclusion, the results were promising, and the method used showed potential considering the wider use of the data processing procedure in the electronics or any other industry. View full abstract»

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  • Statistical Analysis of Transponder Packaging in UHF RFID Systems

    Page(s): 97 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1355 KB) |  | HTML iconHTML  

    Packaging of RFID transponders that operate at ultrahigh frequencies (UHF) requires nontraditional materials and innovative methods in order to make a functional, reliable, and inexpensive RFID transponders. Presented is a statistical analysis along with the model as the way to evaluate measured results and provide the quality and process control for the electrical and mechanical performance of the packaging of RFID tags with respect to different manufacturing processes. The power analysis is presented in support of the statistical analysis and the sample size selection. View full abstract»

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  • Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

    Page(s): 106 - 114
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    The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies. View full abstract»

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  • An Empirical Comparison of Spatial Randomness Models for Yield Analysis

    Page(s): 115 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1039 KB) |  | HTML iconHTML  

    Yield analysis is an important activity in the assessment and control of semiconductor fabrication processes. Tests of spatial randomness provide a means of enhancing yield analysis by considering the patterns of good and defective chips on the wafer. These patterns can be related to the likely sources of defects during production. This paper compares two approaches for determining spatial randomness based on join-count statistics. The first assumes that a random distribution of defects can be modeled as a spatially homogenous Bernoulli process (SHBP). The second uses a Markov random field (MRF) as the null distribution. While both methods are shown to have good performance, the MRF outperforms the SHBP on both clustered and random defect data. View full abstract»

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  • Table of contents

    Page(s): 121 - 122
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  • Table of contents

    Page(s): 123 - 124
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  • IEEE Components, Packaging, and Manufacturing Technology Society information for authors

    Page(s): C3
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information

    Page(s): C4
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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

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Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University