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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 3 • Date March 2009

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Displaying Results 1 - 21 of 21
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • A New Loss Compensation Technique for CMOS Distributed Amplifiers

    Page(s): 185 - 189
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB) |  | HTML iconHTML  

    This brief presents a circuit technique to compensate for the metal and substrate loss of the on-chip transmission lines (TLs), and, consequently, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). An eight-stage DA suitable for 40-Gb/s optical communication is devised and implemented in a 0.13-mum CMOS process. The DA achieves a flat gain of 10 dB from dc to 44 GHz with an input and output matching better than -8 dB. The measured noise figure varies from 2.5 to 7.5 dB with the amplifier's band. The proposed DA dissipates 103 mW from two 1-V and 1.2-V dc supplies. View full abstract»

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  • On the Attenuation of DAC Aliases Through Multiphase Clocking

    Page(s): 190 - 194
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (561 KB) |  | HTML iconHTML  

    ldquoL-foldrdquo interpolation can be used to lower aliases of digital-to-analog converters (DACs). L-fold interpolation uses multiple DACs, each clocked with different phases of a single clock frequency with each DAC using the same signal data. The literature on this topic indicates that lowering the aliases can only be done by increasing the number of DACs and clock phases. This brief shows that by proper selection of clock phases, precise cancelling of certain aliases for a two-phase clock with two DACs is already possible. The cancellation of aliases helps reduce unwanted spurious emissions when DACs are used as amplitude modulators in polar transmitters. View full abstract»

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  • A Low-Leakage Open-Loop Frequency Synthesizer Allowing Small-Area On-Chip Loop Filter

    Page(s): 195 - 199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    A frequency synthesizer targeting low-power packet-based frequency-shift-keying (FSK) applications using open-loop modulation of the oscillator is presented. Unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. It is, therefore, possible to use a wide loop-filter bandwidth without violating the noise or spurious requirements. A wideband loop-filter can be implemented using small component values, allowing an on-chip loop filter. To handle the frequency drift associated with open-loop implementations, a low-leakage charge pump is proposed. The synthesizer is implemented using a 0.18-mum CMOS process. The total power consumption is 9 mW, and the circuit area including the voltage-controlled oscillator (VCO) inductors and on-chip loop-filter is 0.32 mm2. The measured frequency drift indicates a leakage current of below 2 fA. View full abstract»

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  • A CMOS Ultra Low-Power and Highly Efficient UWB-IR Transmitter for WPAN Applications

    Page(s): 200 - 204
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    This brief presents an on-off LC oscillator-based ultrawideband impulse radio (UWB-IR) transmitter for long-range application. A thorough theoretical analysis of the pulse generation is provided. Implemented in a 0.18-mum CMOS, the transmitter works in the UWB lower band of 3-5 GHz and consumes an ultralow average power of 236 muW at 1.8-V power supply. UWB pulses with a bandwidth of 2 GHz and 10-dB sidelobe suppression are generated. The transmitter can deliver a large differential output swing of 4.9 V under 100-Omega load with the highest power efficiency of 25.4% to date. It is targeted for wireless sensor network (WSNs) and wireless personal area network (WPAN) applications. View full abstract»

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  • Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration

    Page(s): 205 - 209
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (774 KB) |  | HTML iconHTML  

    This brief presents an adaptive-bandwidth (BW) phase-locked loop (PLL) that retains the optimal jitter performance over a wide frequency range via continuous background frequency calibration. The effective center frequency of the voltage-controlled oscillator (VCO) is calibrated by adjusting the feedforward division factor while a dual-PLL architecture hides the switching transients. As a result, the core ring oscillator only needs to operate over a narrow frequency range of 2 : 1 that is optimal for the jitter, supply sensitivity, and charge pump current mismatch over process, voltage, and temperature (PVT) conditions. The prototype PLL was fabricated in a 0.13-mum CMOS process, consumed 36 mW of power, and occupied 1.1 x 0.46 mm2 of area. The measured root-mean-square (RMS) tracking jitter was less than 0.2% of the reference clock period for the wide range of output frequency (2 MHz-1 GHz) and multiplication factor (20-9), which supports that the PLL BW scales adaptively with the reference frequency. Compared to a PLL without frequency calibration, the proposed PLL demonstrated the jitter reduction up to 80%. View full abstract»

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  • A Synchronous Multioutput Step-Up/Down DC–DC Converter With Return Current Control

    Page(s): 210 - 214
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB) |  | HTML iconHTML  

    This brief presents a new return-current control method for a multioutput step-up/down dc-dc converter. Compared with prior multioutput dc-dc converters, the presently described converter can generate outputs higher or lower than the input voltage with simple control-loop compensation while guaranteeing stability in a wide load range. Using a 0.5-mum bipolar CMOS (BiCMOS) process, a converter having five outputs has been implemented for an LG active-matrix organic light-emitting diode (AM-OLED) display panel. The implemented converter operates at 1-MHz switching frequency with 4.7- muH inductor and 10-muF capacitor. Experimental results show that the proposed control method can generate tightly regulated stepped-up or -down outputs stably under a wide load variation. The conversion efficiency is higher than 80% at a typical AM-OLED panel grey level. View full abstract»

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  • Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

    Page(s): 215 - 219
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    In this brief, a new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed. Employing the proposed algorithm, the hardware complexity of the controller of shuffle networks using the Benes network structure can be significantly reduced. In addition, a low-complexity reconfigurable shuffle network architecture for flexible LDPC decoders is developed. Both the Benes network and the controller can be tailored to fit specific applications. Consequently, an efficient shuffle network for WiMAX LDPC decoders is presented. Synthesis results demonstrate that with the SMIC 0.18-mum complementary metal-oxide-semiconductor process, the total gate count of the proposed shuffle network is only 16 000. The area saving is between 26.6% and 71.1% compared to related works in the literature. View full abstract»

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  • WLS Design of Variable Fractional-Delay FIR Filters Using Coefficient Relationship

    Page(s): 220 - 224
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    In this brief, a new coefficient relationship is proposed for the design of variable fractional-delay (VFD) finite-impulse response (FIR) filters by the weighted least-squares (WLS) method so that the number of filter coefficients to be designed can approximately be halved. To reduce the computational cost, closed-form expressions for the elements of related vectors and matrices are derived. Several design examples are presented, and the comparisons show that the overall performance of the proposed method is comparable with that of the conventional method; however, the number of filter coefficients to be designed for the proposed method is about half of that in the conventional method. View full abstract»

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  • Periodic Input Response of a Second-Order Digital Filter With Two's Complement Arithmetic

    Page(s): 225 - 229
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    The dynamic behaviors of a nonlinear second-order digital filter with two's complement arithmetic under periodic inputs are explored. The conditions for avoiding overflow are derived. Various dynamic periodic responses are analyzed, accompanied by numerous simulation examples. View full abstract»

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  • Asymmetrical Oscillations in Digitally Controlled Power-Factor-Correction Boost Converters

    Page(s): 230 - 234
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (519 KB) |  | HTML iconHTML  

    Digitally controlled power-factor-correction (PFC) converters are essentially piecewise-smooth nonlinear systems due to their switching action. However, their complex behavior almost remains unexplored. Unlike analog control, digital control introduces a time delay due to the sample-and-hold and the digital computation. Here, a small-signal model that takes the time delay into account is derived to judge the stability of a digitally controlled PFC boost converter. It is proven that the time delay seriously degrades the converter's stability. After the inner current loop and/or the outer voltage loop lose stability, we experimentally discover that oscillations begin to occur, and the oscillations are asymmetrical. Such an asymmetry can be interpreted by the underdevelopment characteristic of the dynamical behavior in the digitally controlled PFC boost converter. The results reported in this brief offer more knowledge about the dynamical behavior in digitally controlled PFC converters. View full abstract»

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  • Pinning Control of Uncertain Complex Networks to a Homogeneous Orbit

    Page(s): 235 - 239
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    A sufficient condition for the stability of uncertain complex networks is derived in terms of linear matrix inequalities based on the V-stability tool, which associates the self-dynamics of nodes with passivity degrees. Then, a pinning control strategy is proposed on the developed condition to stabilize the uncertain complex networks to a homogenous orbit. As an illustrative example, a network with the Lorenz system as node self-dynamics is simulated to verify the analytic results. View full abstract»

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  • Convergence Analysis of Teleoperation Systems With Unsymmetric Time-Varying Delays

    Page(s): 240 - 244
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB) |  | HTML iconHTML  

    This brief addresses the stability problem of a class of teleoperation systems. Compared with previous work, the communication delays are assumed to be both time varying and unsymmetric. We consider the usual case that the master and the slave manipulators are coupled using a proportional-derivative (PD) control strategy. By using a new Lyapunov-Krasovskii functional, we show that the master-slave teleoperation system is asymptotically stable under specific linear matrix inequality (LMI) conditions. With the given PD parameters, the values of allowable maximum time delays can be obtained. Finally, simulations are performed to show the effectiveness of the proposed method. View full abstract»

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  • Design, Analysis, and Experimentation of Chaotic Permanent Magnet DC Motor Drives for Electric Compaction

    Page(s): 245 - 249
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    In this brief, a new electrically chaotic permanent magnet dc motor drive is designed, analyzed, and implemented for electric compaction. The key is to newly apply chaotic speed reference control to the torque controller of the motor drive, which, in turn, generates chaotic motion for the compactor. The proposed electric chaoization not only offers the advantages of lighter weight, smaller size, and higher controllability, compared with its mechanical counterpart, but also provides higher flexibility and better accuracy, compared with previous electric chaoizing approaches. By numerically comparing the compaction performance, i.e., the average compaction energy density, the proposed chaotic compactor is more effective than the conventional compactors using constant input voltage control and sinusoidal speed reference control. After prototyping, experimentation is performed to verify the validity of the proposed compactor. View full abstract»

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  • New Delay-Dependent Global Exponential Stability Criterion for Cellular-Type Neural Networks With Time-Varying Delays

    Page(s): 250 - 254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB) |  | HTML iconHTML  

    The problem ensuring the global exponential stability (GES) of a class of delayed cellular neural networks (CNNs) with time-varying delays is studied. Without assuming the boundedness of the activation functions, by applying the idea of the Lyapunov function, the linear matrix inequality (LMI) techniques, the free-weighting matrix method, and a novel equation, a new sufficient condition for the GES of CNNs with time-varying delays is obtained, which generalizes the previous results in the literature. The criterion is easy to be verified since it takes the form of an LMI. Three numerical examples are given to illustrate the effectiveness and less conservativeness of our proposed method. View full abstract»

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  • Protocol and Fault Detection Design for Nonlinear Networked Control Systems

    Page(s): 255 - 259
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (134 KB) |  | HTML iconHTML  

    This brief considers the problem of fault detection (FD) for a class of nonlinear networked control systems (NCSs) in which the sensors and actuators of the plant exchange information with a remote controller via a shared communication medium. Under the model utilized here, the communication cannot transfer all the information that sensors or controllers send. The choice of sensors and actuators that are active is designed to achieve the reachability and observability of the NCS. A novel method is proposed for the FD of a nonlinear NCS by first identifying a pair of communication sequences that preserve reachability and observability and then designing an observer-based FD based on those sequences. An example is given to show the potential of the proposed techniques. View full abstract»

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  • Corrections to “VLSI Design of Diminished-One Modulo 2^{n} + 1 Adder Using Circular Carry Selection” [Sep 08 897-901]

    Page(s): 260 - 261
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB)  

    In a recent paper by Lin and Sheu, the authors have proposed a new circular-carry-selection technique that is applied in the design of an efficient diminished-one modulo 2n + 1 adder. The proposed modulo adder in the aforementioned paper consists of a dual-sum carry look-ahead (DS-CLA) adder, a circular carry generator, and a multiplexer, which can reduce both area-time (AT) and time-power (TP) products compared with previous modulo adders. However, in our investigation, there will be incorrect results on the calculation of modulo addition because the carry-in of the DS-CLA adder is equal to zero. To remedy this drawback, we propose the corrected architecture of the DS-CLA adder based on the equations proposed in the aforementioned paper, which can perform correct modulo addition. The complexity of the corrected architecture is almost the same as the one proposed by Lin and Sheu but with less area cost, which can also have the same merits of both AT and TP products. View full abstract»

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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): 262
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Freely Available from IEEE
  • IEEE copyright form

    Page(s): 263 - 264
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Page(s): C3
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    Freely Available from IEEE

Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope