IET Computers & Digital Techniques

Issue 2 • March 2009

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Displaying Results 1 - 7 of 7
  • Reconfigurable broadcast scan compression using relaxation-based test vector decomposition

    Publication Year: 2009, Page(s):143 - 161
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (690 KB)

    An effective reconfigurable broadcast scan compression scheme that employs partitioning of test sets and relaxation-based decomposition of test vectors is proposed. Given a constraint on the number of tester channels, the technique classifies test sets into acceptable and bottleneck vectors. The bottleneck vectors are then decomposed into a set of vectors that meets the given constraint. The accep... View full abstract»

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  • Interconnect and communication synthesis for distributed register-file microarchitecture

    Publication Year: 2009, Page(s):162 - 174
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (783 KB)

    Distributed register-file microarchitecture (DRFM), which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data-routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on-chip memory or register-file IP blocks. In comparison with the discrete-register-based architecture, DRF... View full abstract»

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  • Droop sensitivity of stuck-at fault tests

    Publication Year: 2009, Page(s):175 - 193
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (203 KB)

    In nanometer-scale integrated circuits, simultaneous switching at gates in physical proximity may induce power supply droop, and thereby invoke timing faults, termed as droop faults. During at-speed testing of such chips, two test vectors in a test sequence may excite droop and, thus, cause test invalidation. Fast application of test vectors may be needed for high-speed testing or for built-in sel... View full abstract»

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  • Design networks-on-chip with latency/ bandwidth guarantees

    Publication Year: 2009, Page(s):184 - 194
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (283 KB)

    A method is proposed to guarantee bandwidth (BW) or latency of network-on-chip. This method contains three kernels: traffic classification; flit-based switching; path pre-assignment and link-BW setting. Compared with the traditional circuit-switch method, the proposed method can guarantee the latency between one flit's generation in the source node and its reception in the destination node. This m... View full abstract»

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  • Utilisation of inverse compatibility for test cost reductions

    Publication Year: 2009, Page(s):195 - 204
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (208 KB)

    Utilisation of input compatibilities alleviates test costs in many applications such as reducing linear feedback shift register (LFSR) size, and scan tree construction among others. Correlation among inputs, identified based on a test set analysis, can be exploited by driving the circuit inputs through fewer channels. The reduction in the number of channels, which is dictated by the number of comp... View full abstract»

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  • High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms

    Publication Year: 2009, Page(s):205 - 221
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (821 KB)

    Considering the time-to-market restrictions and the increased computational complexity of modern applications, the efficient design of data intensive digital signal processing (DSP) applications is a challenging problem. A typical design exploration procedure, which uses simulation-based tools for various cache parameters, is a rather time-consuming task, even for low-complexity applications. The ... View full abstract»

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  • Test vector chains for increasing the fault coverage and numbers of detections

    Publication Year: 2009, Page(s):222 - 233
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (194 KB)

    The authors introduce the concept of test vector chains which allows one to obtain new test vectors from existing ones through single-bit changes. A test vector chain is defined based on a pair of test vectors t 1 and t 2. It consists of a sequence of single-bit changes, which gradually modifies t 1 into t 2. The authors demon... View full abstract»

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IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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