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Components and Packaging Technologies, IEEE Transactions on

Issue 1 • Date March 2009

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Displaying Results 1 - 25 of 35
  • [Front cover]

    Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Components and Packaging Technologies publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1 - 2
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  • Internal Geometry Variation of LTCC Inductors to Improve Light-Load Efficiency of DC-DC Converters

    Page(s): 3 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1243 KB) |  | HTML iconHTML  

    A low-profile power inductor fabricated using low-temperature cofired ceramic (LTCC) technology has been demonstrated to improve the light-load efficiency of a converter, without the use of additional control circuitry. This is brought about by the material and the geometry, which causes a change in inductance with load current. Variation in inductor geometry is performed experimentally to study the effects on the light-load efficiency of a converter. By decreasing the conductor width of the inductor, the light-load efficiency can be further improved by 30% in comparison with using commercial inductors of similar inductance. Sufficient core thickness is necessary to have sufficient inductance, since an inductance value which is too low is detrimental from the system power loss point of view, as demonstrated experimentally. From the circuit point of view, there seems to be a critical inductance value, whereby increasing the inductance further, does not result in significant improvement in power stage efficiency. Changing conductor thickness in the range of 260 to 550 mum does not result in significant improvement in the overall efficiency of the converter. Variation in the number of parallel conductors in a multiconductor structure does not have significant effect on light-load efficiency improvement. View full abstract»

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  • Thermomechanical Analysis of Plastic Ball Grid Arrays With Vapor Pressure Effects

    Page(s): 12 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (591 KB) |  | HTML iconHTML  

    This study adopts a mechanism-based computational approach to gain insights into the delamination and cracking of plastic ball grid array (PBGA) packages under moisture sensitivity test (MST) conditions. The possible crack paths in the molding compound are first examined by modeling the fully porous over-mold with void-containing cell elements. These computational cells are governed by a Gurson constitutive relation, extended to account for vapor pressure effects. We show that the corner of the die/die-attach interface presents a likely site for crack initiation under MST conditions. Failure along this interface of interest is then examined by deploying a single row of computational cells along the die/die-attach interface. Under combined thermal and vapor pressure loading, delamination concurrently occurs at both the die corner and the die center; these competing damage sites lead to the rapid and complete delamination of the die/die-attach interfaces. View full abstract»

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  • Fabrication and Characterization of a Low-Cost, Wafer-Scale Radial Microchannel Cooling Plate

    Page(s): 20 - 29
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    The modeling, simulation, fabrication, and testing of a microchannel cooling plate for microelectronic packaging applications are described in this paper. The cooling component uses forced convection of gas injected inside 128 microchannels of 100-mu m width and 70-mu m height. The nickel-based plate is fabricated on a glass substrate using a two-layer electroforming process using UV-LIGA technology. The thermal behavior of the microchannel cooling device is investigated by using the measurement of partial thermal resistances through the use of the structure functions method. Heat transfer coefficient values of 300 W/m2 K have been measured for a nitrogen flow rate of 120 l/h. View full abstract»

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  • Asynchronous Modular Contactor for Intelligent Motor Control Applications

    Page(s): 30 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1388 KB) |  | HTML iconHTML  

    R&D activities have been carried out for decades by many researchers in order to improve electromechanical contactor performance employing electronic control. This includes electronic controlled contactor opening to minimize contact erosion, and closing to reduce contact bounce, but the improvement is limited with significant increase of cost and size due to the inherent design structure of contactors: simultaneously switching of all three poles. Meanwhile, solid-state motor starters have shown great benefit with point-on-wave (POW) switch-on to minimize transient current and torque stress of induction machines during motor starting process. However, cost and size is a premium. A novel technology that employs asynchronous modular concept and POW switching has been developed. This improves motor starting and contactor switching performances in respect to switching transients and contact erosion while utilizing small size and low cost electromechanical contactors. These contactors are assembled into a flexible modular contactor assembly that allows each pole to be switched independently with precise POW switching control. This paper will focus on motor starting applications to achieve significant reduction of motor starting transients and contactor switching capability improvement. Asynchronous modular contactor prototypes with newly developed 24-VDC controlled contactors have been developed. The evaluation tests of the prototype proved significant transient current and torque stress reduction during motor starting. View full abstract»

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  • Computational Assessment of the Effects of Temperature on Wafer-Level Component Boards in Drop Tests

    Page(s): 38 - 43
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    The drop reliability of wafer-level chip-scale package (WL-CSP) component boards used in portable devices was studied by employing mechanical shock loads (JESD22-B111 standard) at different temperatures. The drop tests were carried out at room temperature (23 degC), 75 degC, 100 degC, and 125 degC. The elevated temperatures were achieved by integrated heater elements in the components. The number of drops-to-failure increased significantly with increasing temperature. The physical failure analysis revealed that the outermost solder interconnections at the four corners of the components failed from the component side. At room temperature, the cracks propagated solely along the intermetallic layers but the increase of testing temperature progressively changed their propagation paths from the intermetallic layers into the bulk solder. Since the temperature 1) decreases the strength and elastic modulus of solders, 2) diminishes the stiffness of printed wiring boards, and 3) introduces thermally induced stresses, the finite-element method was employed to evaluate their combined effects. The calculations showed that due to the increases in testing temperature, the peeling stress is reduced markedly, while the equivalent plastic strain is only slightly increased at the interfacial regions of the solder interconnections. The reduction of the stresses increases the proportion of the bulk solder cracking relative to the cracking of the intermetallic layers and therefore the number of drops-to-failure increases as a function of increasing test temperature. View full abstract»

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  • Optimization of Cylindrical Pin-Fin Heat Sinks Using Genetic Algorithms

    Page(s): 44 - 52
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    In this paper, genetic algorithms (GAs) are applied for the optimization of pin-fin heat sinks. GAs are usually considered as a computational method to obtain optimal solution in a very large solution space. Entropy generation rate due to heat transfer and pressure drop across pin-fins is minimized by using GAs. Analytical/empirical correlations for heat transfer coefficients and friction factors are used in the optimization model, where the characteristic length is used as the diameter of the pin and reference velocity used in Reynolds number and pressure drop is based on the minimum free area available for the fluid flow. Both inline and staggered arrangements are studied and their relative performance is compared on the basis of equal overall volume of heat sinks. It is demonstrated that geometric parameters, material properties, and flow conditions can be simultaneously optimized using GA. View full abstract»

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  • Thermal and Mechanical Characteristics of a Multifunctional Thermal Energy Storage Structure

    Page(s): 53 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (706 KB) |  | HTML iconHTML  

    Thermal energy storage (TES) sandwich-structures that combine the heat storage function with structural functionality are described. The structure consists of a thermal interface (TI) connected to a hollow plate lamination. Each laminate is a hollow aluminum plate having a series of mm-scale channels or compartments that are filled with phase change material (PCM). Heat storage is via the latent heat of the PCM. A generalized thermal response model that is applicable to a wide range of channel geometrical configurations is described. The model couples the thermal response of the TI to the hollow aluminum plate/PCM-volume. The temporal response of the system is easily obtained via numerical solution of two ordinary differential equations, which can be solved to give closed-form solutions subject to a simple assumption. Thermal analysis delineates geometrical configurations that have good thermal response characteristics. The mechanical properties of the laminated structure are determined experimentally. Four-point bending experiments are conducted using specimens made with three layers of hollow plates laminated using a structural adhesive. An energy method is developed to model both the deformation and strength of the laminated structure. The energy method is developed based on the assumption that plane cross sections of the structure remain plane under bending, a condition that is valid for both linear and nonlinear materials. The energy method can provide deformation of the aluminum laminates comparable with the experiments. Experiments and modeling indicate that these laminated structures have an excellent performance-to-weight ratio. View full abstract»

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  • Simulation and Optimization of Gate Temperatures in GaN-on-SiC Monolithic Microwave Integrated Circuits

    Page(s): 63 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB) |  | HTML iconHTML  

    This paper presents 3-D thermal simulation studies of GaN-on-SiC monolithic microwave integrated circuits (MMICs) containing multifinger micrometer-scale high electron mobility transistors (HEMTs). The heat spreading effect of HEMT source, gate, and drain metallizations on peak structure temperatures is examined. The impacts of a realistic die attach material and rear-of-die heat transfer coefficient on structure temperatures, and in particular on temperature nonuniformity, are examined. Variable gate finger spacing, in which the gate spatial positions are described by polynomials as a function of gate number, is investigated as a means for optimizing the temperature uniformity from gate-to-gate. A thermal simulation code with a parametric MMIC geometry-based mesh generator and a deformable mesh consistent with sequential movement of gate finger positions during optimization is employed for all of the studies. The code is multiscale with a sufficient resolution range to handle a multifinger HEMT structure while also including the MMIC die, die attach metallization, and a realistic heat transfer coefficient associated with microchannel coolers. A variable gate pitch geometry based on an optimized cubic polynomial demonstrates considerable advantage in temperature uniformity. View full abstract»

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  • Dependence of the Fracture of PowerTrench MOSFET Device on Its Topography in Cu Bonding Process

    Page(s): 73 - 78
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    Dependence of the fracture-resistance of a PowerTrench MOSFET device on its topography in Cu bonding process was investigated. Two different topographies, namely dimple and round, have been tested. A significantly higher cratering rate has been clearly observed on dimple topography. The dimple topography exhibited a cratering rate of 371 k ppm levels compared to 0 ppm in round topographies. Three-dimensional nonlinear finite-element analysis has shown that the largest compressive and shear stresses and their locations were identified, respectively, in borophosphosilicate glass (BPSG)/barrier metal layers of the dimple topography. The round topography had the smallest stress in BPSG/barrier metal layers. The higher compressive stress transferred to silicon in the dimple topography during the bonding process can induce a local crack, consequently causing silicon fracturing during the shearing processes. A significant improvement in the cratering performance was observed when the Al bond pad metal layer was reinforced by adding a barrier layer sandwiched in the Al metal layers. The cratering rate decreased to 1300 ppm levels. Additionally, the change in composition of a BPSG layer caused cratering was briefly discussed and an oxygen rich BPSG film in round topography was confirmed by the energy dispersive spectroscopy (EDS) of a cross-sectional TEM sample. It has been found that the cratering rate on dimple topography significantly increased from 1 k ppm to 100 k ppm levels, when the resulting residual Al pad thickness is less than 0.65 mum for Cu bonding performed with different ultrasonic (US) power and bond forces. View full abstract»

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  • Electromigration Test on Void Formation and Failure Mechanism of FCBGA Lead-Free Solder Joints

    Page(s): 79 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1860 KB) |  | HTML iconHTML  

    The effect of electromigration (EM) on void formation and the failure mechanism of flip chip ball grid array (FCBGA) packages under a current density of 1 -10 A/cm2 and an environmental temperature of 150degC was investigated. Eight solder/substrate combinations of four lead-free solder systems with two substrates were examined to verify the failure modes. A conservative failure criterion was adopted to define and predict the failure of the package, scanning electron microscope (SEM) was employed to observe in situ microstructural changes, intermetallic compound (IMC) growth, and failure modes. All samples exhibited a similar failure, attributed mainly to void occupation along under bump metallization (UBM)/solder interfaces at the cathode chip side of the bumps with downward electron flow. Voids were initiated at the corner due to current crowding. Two specific void locations were identified at the IMC/solder and UBM/IMC interfaces, and they coexisted in the same specimen but in different bumps. No void coupling mode was found. Since the atom diffusion rate in the solder differs from that in the IMC layer, the voids can be formed between them. A current density of 1-104 A/cm2 was sufficiently high to form a void pattern at the IMC/solder interface. However, the formation of voids at the UBM/IMC interface is generally induced by the consumption of UBM, since the high temperature of 150degC crucially dominates the void morphology at the UBM/IMC interface. The difference among solder systems did not affect the failure modes nor dominate mechanisms. With respect to the differences of substrate surface finishes, more voids appeared at the cathode substrate side of the solders combined with Cu/Ni/Au pad than those combined with copper-organic solderable preservative (Cu-OSP) after long-term upward electron stressing. It suggested another possible failure at the substrate side when failure did not occur at the chip side in an EM test. View full abstract»

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  • Thermal Management of Blocks in a Channel Using Phase Change Material

    Page(s): 89 - 99
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    The application of the phase change material (PCM) in thermal management of an electronic device is presented in this paper. The considered geometry consists of a horizontal channel with three volumetrically heated blocks mounted on the bottom wall of the channel in a forced convection domain. The heated blocks simulate electronic chips. A PCM layer is attached to the bottom wall of the channel under the blocks. The objective of incorporating PCM into the system is to utilize its low melting temperature and high latent heat of fusion to absorb heat from the blocks during high-power periods, and to maintain their temperature at an acceptable level. The performance of the proposed PCM system is evaluated by comparing thermal characteristics of the system to a system without PCM. The peak temperature of the blocks can be reduced by 13.7%-26.8% for substantial amount of time, depending on the blocks' location in the channel, amount of the PCM utilized, and Reynolds number. Flow streamlines, temperature contours, blocks' peak temperature, and average nusselt temperature are presented. View full abstract»

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  • Development of a Thermal Switch Using the Channel Geometry Effect for Electronic Packages

    Page(s): 100 - 105
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    This paper presents development of a thermal switch using the channel geometry effect for electronic packages operated via liquid conduction channel formation. The developed switch panel is composed of several conduction channels, breathing grooves, reservoirs, and actuators. On demand, a vacant conduction channel is filled with liquid supplied by an actuator and conducts heat from hot spots to cold. This result in increased heat dissipation. Through this switch operation, the temperature of the designated hot spot can be controlled locally. In order to realize the desired switch operation of liquid contact and separation properly, with liquid supplied from a reservoir and returning to the reservoir, the liquid column should be precisely controlled based on the channel design. The conduction channel has a burst area to achieve the precise liquid control. The burst area was geometrically designed to provide a hydrophilic surface by taking into account the burst pressure. In a series of experiments, the newly designed switch was shown in controlling the liquid column well. The results also showed that this thermal switch was able to regulate the heat flow and the temperature distribution locally through the achieved liquid column control. View full abstract»

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  • The Fracture Resistance of Bonded Au Wires for Interconnection

    Page(s): 106 - 109
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    This paper presents the effects of the local strength degradation due to recrystallization and grain growth and the large deformation induced in wire bonding process on the fracture resistance of the bonded Au wires for interconnection. The experimental and numerical results show that, for a wire to deform to the required shape without reduction in the fracture resistance, sufficient ductility is more important than the strength of the wire. View full abstract»

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  • Efficient Fourier Series Solutions to Nonlinear Steady-State Heat Conduction Problems in Microwave Circuits

    Page(s): 110 - 119
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    This paper presents a method of obtaining rapidly convergent Fourier series solutions to heat conduction problems in media containing temperature-dependent and orthotropic thermal conductivities subject to applied surface flux. Such problems occur frequently in the analysis of thermal heating of integrated circuits, with the heat sources consisting primarily of transistors, resistors and other conductors on the top surface of the die. The key development in obtaining improved convergence behavior, relative to similar existing series solutions, is the use of smoothly varying Gaussian distributions for the applied loads versus the more conventional, discontinuous, uniformly applied (isoflux) heat loads. It is shown that the smoothness of a Gaussian distribution effectively suppresses the higher order series expansion coefficients normally introduced by the uniformly applied loads and reduces the number of terms required for convergence by up to 98%. The rate of decay of the series expansion coefficients for three load distributions, with varying degrees of smoothness, and the corresponding rate of convergence of the respective doubly infinite series, are examined in detail. View full abstract»

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  • Study of Flip Chip Solder Joint Cracks Under Temperature Cycling Using a Laser Ultrasound Inspection System

    Page(s): 120 - 126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (925 KB) |  | HTML iconHTML  

    The current techniques for nondestructive quality evaluation of bumped solder joint connections in electronics packages are either incapable of detecting solder joint cracks, or unsuitable for inline inspection due to cost and throughput reasons. As an alternative, a novel solder joint inspection system is being developed. The system projects short laser pulses onto specimen surface through optic fibers to induce structural vibration. The induced surface displacements are then measured by a laser Doppler vibrometer. A number of digital signal processing algorithms, such as error ratio and correlation coefficient, were used to analyze the vibration responses and identify defective specimens. This paper presents a systematic study of parameters such as error ratio, correlation coefficient, resonant frequency, electrical resistance, and the extension of solder joint cracks, to quantitatively characterize the relationships among them. These relationships verified that the laser ultrasound inspection system provides a reliable and efficient way to evaluate flip chip solder joint cracks nondestructively. View full abstract»

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  • An Experimental Study on Minimum Arc Current for Arcs Longer Than a Few Microseconds in Relay Contacts and Possible Reinterpretation of the Meaning Thereof

    Page(s): 127 - 134
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    A minimum arc current value for each contact material is one of the very important factors in consideration and comparison of arc discharge characteristics for proper selection of contact materials. In this paper, Ag and Ag alloy contacts were operated to break various dc load currents in the range of up to 1.5 A with 10-30 V, and occurrence rates of break arcs (having durations equal to or longer than a few microseconds) were investigated at each condition. As a result, it is confirmed that at the conventional minimum arc current level, break arcs on the order of several tens of microseconds occur at occurrence rate close to 100% when sufficient energy is supplied to contacts upon opening. Thus, careful attention should be paid to when using the term ldquominimum arc currentrdquo in order to avoid misinterpretation. View full abstract»

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  • Leading Indicators of Failure for Prognostication of Leaded and Lead-Free Electronics in Harsh Environments

    Page(s): 135 - 144
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    In this paper, a methodology for prognostication-of-electronics has been developed for assessment of residual life in deployed electronic components, and the determination of damage-state in absence of macro-indicators of failure. Proxies for leading indicators-of-failure have been identified and correlated with damage progression under thermomechanical loads. Examples of proxies include micro-structural evolution characterized by average phase size and intermetallic growth rate in solder interconnects. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu lead-free electronics. Structures examined include plastic ball grid array format electronic and MEMS packages and discrete devices assembled with FR4-06 laminates. The focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. Instead of life prediction of new components, the research is aimed at the development of damage relationships for determination of residual life of aged electronics and the assessment of design margins. The prognostic indicators presented in this paper can be used for health monitoring of electronic assemblies. View full abstract»

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  • Detailed CFD Modelling of EMC Screens for Radio Base Stations: A Parametric Study

    Page(s): 145 - 155
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1382 KB) |  | HTML iconHTML  

    The objective of this paper is to make a parametric study of the hydraulic resistance and flow pattern of the flow after an electromagnetic compatibility screen and between two printed circuit boards (PCBs) in a model of a 90deg subrack cooling architecture. The parametric study is carried out using a detailed 3-D model of a PCB slot. The detailed model was experimentally validated in a previous paper by the authors. Seven parameters were investigated: velocity, inlet height, screen porosity, PCB thickness, distance between two PCBs, inlet-screen gap and screen thickness. A correlation for the static and dynamic pressure drop, the percentage of dimensionless wetted area, Aw*, and the RMS* factor (a function of the flow uniformity along the PCB) after the screen is reported as a function of six geometrical dimensionless parameters and the Reynolds number. The correlations, that are based on 174 three dimensional simulations, yield good results for the total pressure drop, in which the values are predicted within the interval of plusmn 15%. For the, Aw*, all the predicted values are within the interval of plusmn22% of the observed values. Finally, for the RMS* factor, the majority of the values also have a disagreement of less than 20% of the observed values. These last two parameters are believed to provide a correct insight about the flow pattern after the screen. View full abstract»

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  • Pool Boiling Experiments on a Nano-Structured Surface

    Page(s): 156 - 165
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    The effect of nano-structured surfaces on pool boiling was investigated. Saturated and subcooled pool boiling experiments were performed on a horizontal heater surface coated with vertically aligned multiwalled carbon nanotubes (MWCNTs). MWCNTs were synthesized using the chemical vapor deposition (CVD) process. In this paper, MWCNT forests of two distinctly different heights (Type A: 9-mum height, and Type B: 25-mu m height) were synthesized separately on silicon wafers. PF-5060 was used as the test liquid. The results show that Type-B MWCNTs yield distinctly higher heat fluxes under subcooled and saturated conditions for both nucleate and film boiling. Type-A MWCNTs provide similar enhancement in nucleate boiling (as Type-B) for both saturated and subcooled conditions. Type-B MWCNTs enhanced critical heat flux (CHF) by 40%. Increasing the height of the MWCNTs is also found to extend the wall super heat required for CHF. In contrast, Type-A MWCNTs provide only marginal enhancement in film boiling compared to bare silicon wafer, for both saturated and subcooled film boiling. Type-B MWCNTs enhanced the heat flux in the film boiling regime for the Leidenfrost point by 175% (compared to bare silicon wafer). View full abstract»

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  • Experimental-Numerical Comparison for a High-Density Data Center: Hot Spot Heat Fluxes in Excess of 500 W/ft ^{2}

    Page(s): 166 - 172
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    This paper uses previously published experimental data to present a comparison between test results and numerical simulations. The example considered is a large 7400 ft2 data canter that houses over 130 heat-producing racks (1.2 MW) and 12 air conditioning units. Localized hot spot heat fluxes were measured to be as high as 512 W/ft2 (5.5 kW/m2 ) for a 400 ft2 (37 m2 ) region. A numerical model based on computational fluid dynamics (CFD) was constructed using inputs from the measurements. The rack inlet air temperature was considered to be the basis for experimental versus numerical comparison. The overall mean rack inlet temperature predicted numerically at a height of 1.75 m is within 4degC of the test data with a rack-by-rack standard deviation of 3.3degC. View full abstract»

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  • The Role of Aging on Dynamic Failure Envelopes of OSP-Sn37Pb Interconnects in Plastic Ball Grid Array (PBGA) Packages

    Page(s): 173 - 179
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB) |  | HTML iconHTML  

    This paper quantifies the effect of aging on the durability of printed wiring assemblies (PWAs) subjected to dynamic loading conditions. The test specimen is a FR4 board with a single 256 I/O, full grid, PBGA component at the center. The pad finish on the board and component side of the Sn37Pb eutectic solder interconnects is organic solderability preservative (OSP) and Sn15Pb, respectively. The test matrix is designed to cover one order of magnitude of PWA flexural strain (1E-3 to 1E-2), three orders of magnitude of PWA flexural strain rate (1E-3 to 1E0 s-1), and two aging conditions (as-reflowed and 125 degC for 100 h). Fatigue failure envelopes, based on a mechanics-inspired empirical rate-dependent model, are used to characterize the durability in terms of PWA flexural strain and strain rate. A failure site transition zone (FSTZ) is defined in terms of the damage parameters, beyond which the failure site changes from the solder to other parts of the PWA. The combined effect of load amplitude, loading rate, and thermal aging on the FSTZ and solder durability is quantified and presented. View full abstract»

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  • Effect of Vapour Force at the Blow-Open Process in Double-Break Contacts

    Page(s): 180 - 190
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1031 KB) |  | HTML iconHTML  

    This paper presents results of a theoretical and experimental investigation of the phenomena of electrical contact repulsion and its associated blow-off characteristics at high current. The voltage and current waveforms as well as contact's displacement oscillograms are recorded for analysis. The mathematical model of the phenomena based on differential equations for the arc, forces, contact heating and evaporation and displacement of the movable contact piece is elaborated to describe repulsion dynamics. All stages of contact separation including opening start, Joule explosion of the constriction zone and arcing are considered in series. It is found that side by side with electromagnetic force, which is responsible for the initiation of contact opening, thermal force due to vapour pressure, which develops further contact separation, is also very important and should be taken into consideration. Dependence of thermal force on voltage, current, circuit parameters and properties of contact material are calculated theoretically and examined against data obtained experimentally for the asymmetric contact pair AgC-AgNi. View full abstract»

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Aims & Scope

IEEE Transactions on Components and Packaging Technologies publishes research and applications articles on the modeling, building blocks, technical infrastructure, and analysis underpinning electronic, photonic, MEMS and sensor packaging.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Koneru Ramakrishna
Freescale Semiconductor, Inc.