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Micro, IEEE

Issue 1 • Date Jan.-Feb. 2009

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Displaying Results 1 - 21 of 21
  • [Front cover]

    Publication Year: 2009 , Page(s): c1
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    Freely Available from IEEE
  • [Front cover]

    Publication Year: 2009 , Page(s): c2
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  • Contents

    Publication Year: 2009 , Page(s): 1 - 2
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  • Symptoms of Healthy Innovativeness

    Publication Year: 2009 , Page(s): 3 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3386 KB) |  | HTML iconHTML  

    What are the symptoms of health in an innovative industry? This seemingly simple question isn't so easy to answer in the midst of a downturn, nor will it be easy to answer over the next year as high tech consolidates through exit and merger. Consolidation will lead to concentration, or what we might call pockets of monopoly. Monopolies tend not to be the most innovative organizations on the planet. Economics teaches us to look for different symptoms. So, the real question isn't what are the symptoms, but rather how will we recognize symptoms of health in an innovative industry when we see them? This paper focuses on three symptoms. View full abstract»

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  • Top Picks from the 2008 Computer Architecture Conferences

    Publication Year: 2009 , Page(s): 6 - 9
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  • Larrabee: A Many-Core x86 Architecture for Visual Computing

    Publication Year: 2009 , Page(s): 10 - 21
    Cited by:  Papers (74)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic. This increases the architecture's programmability as compared to standard GPUs. The article describes the Larrabee architecture, a software renderer optimized for it, and other highly parallel applications. The article analyzes performance through scalability studies based on real-world workloads. View full abstract»

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  • Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers

    Publication Year: 2009 , Page(s): 22 - 32
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1257 KB) |  | HTML iconHTML  

    Uncontrolled interthread interference in main memory can destroy individual threads' memory-level parallelism, effectively serializing the memory requests of a thread whose latencies would otherwise have largely overlapped, thereby reducing single-thread performance. The parallelism-aware batch scheduler preserves each thread's memory-level parallelism, ensures fairness and starvation freedom, and supports system-level thread priorities. View full abstract»

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  • Cost-Efficient Dragonfly Topology for Large-Scale Systems

    Publication Year: 2009 , Page(s): 33 - 40
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB) |  | HTML iconHTML  

    It is more efficient to use increasing pin bandwidth by creating high-radix routers with a large number of narrow ports instead of low-radix routers with fewer wide ports. building networks using high-radix routers lowers cost and improves performance, but also presents many challenges. the dragonfly topology minimizes network cost by reducing the number of global channels required. View full abstract»

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  • Server Designs for Warehouse-Computing Environments

    Publication Year: 2009 , Page(s): 41 - 49
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB) |  | HTML iconHTML  

    The enormous scale of warehouse-computing environments leads to unique requirements in which cost and power figure prominently. Models and metrics quantifying these requirements, along with a benchmark suite to capture workload behavior, help identify bottlenecks and evaluate solutions. A holistic approach leads to a new system architecture incorporating volume non-server-class components in novel packaging solutions, with memory sharing and flash-based disk caching. View full abstract»

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  • Using Intradisk Parallelism to Build Energy-Efficient Storage Systems

    Publication Year: 2009 , Page(s): 50 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    Server storage systems use numerous disks to achieve high performance, thereby consuming a significant amount of power. This paper discussed the intradisk parallelism that can significantly reduce such systems' power consumption by letting disk drives exploit parallelism in the I/O request stream. By doing so, it's possible to match, and even surpass, a storage array's performance for these workloads using a single, high-capacity disk drive. View full abstract»

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  • Flexible Hardware Acceleration for Instruction-Grain Lifeguards

    Publication Year: 2009 , Page(s): 62 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB) |  | HTML iconHTML  

    Instruction-grain lifeguards monitor executing programs at the granularity of individual instructions to quickly detect bugs and security attacks, but their fine-grain nature incurs high monitoring overheads. This article identifies three common sources of these overheads and proposes three techniques that together constitute a general-purpose hardware acceleration framework for lifeguards. View full abstract»

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  • Atom-Aid: Detecting and Surviving Atomicity Violations

    Publication Year: 2009 , Page(s): 73 - 83
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1005 KB) |  | HTML iconHTML  

    Hardware can play a significant role in improving reliability of multithreaded software. Recent architectural proposals arbitrarily group consecutive dynamic memory operations into atomic blocks to enforce coarse-grained memory ordering, providing implicit atomicity. The authors of this article observe that implicit atomicity probabilistically hides atomicity violations by reducing the number of interleaving opportunities between memory operations. They propose atom-aid, which creates implicit atomic blocks intelligently instead of arbitrarily, dramatically reducing the probability that atomicity violations will manifest themselves. View full abstract»

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  • SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization

    Publication Year: 2009 , Page(s): 84 - 95
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (566 KB) |  | HTML iconHTML  

    Many code analysis techniques for optimization, debugging, and parallelization must perform runtime disambiguation of address sets. Hardware signatures support such operations efficiently and with low complexity. SoftSig exposes hardware signatures to software through instructions that control which addresses to collect and which to disambiguate against. The Memoise algorithm demonstrates SoftSig's versatility by detecting and eliminating redundant function calls. View full abstract»

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  • Trading Off Cache Capacity for Low-Voltage Operation

    Publication Year: 2009 , Page(s): 96 - 103
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1455 KB) |  | HTML iconHTML  

    Two proposed techniques let microprocessors operate at low voltages despite high memory-cell failure rates. They identify and disable defective portions of the cache at two granularities: individual words or pairs of bits. Both techniques use the entire cache during high-voltage operation while sacrificing cache capacity during low-voltage operation to reduce the minimum voltage below 500 mV. View full abstract»

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  • Mixed-Signal Approximate Computation: A Neural Predictor Case Study

    Publication Year: 2009 , Page(s): 104 - 115
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1353 KB) |  | HTML iconHTML  

    As transistors shrink and processors trend toward low power, maintaining precise digital behavior grows more expensive. Replacing digital units with analog equivalents sometimes allows similar computation to be performed at higher speed using less power. As a case study in mixed-signal approximate computation, the authors describe an enhanced neural prediction algorithm and its efficient analog implementation. View full abstract»

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  • Temperature Variation Characterization and Thermal Management of Multicore Architectures

    Publication Year: 2009 , Page(s): 116 - 126
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3181 KB) |  | HTML iconHTML  

    Increased variability affects the efficiency of dynamic power and thermal management. Existing on-chip sensor infrastructure can be used to improve the inherent thermal imbalances among cores in a multicore architecture. Experimental analysis based on live measurements on a special test chip shows reduced on-chip heating with no performance loss. View full abstract»

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  • Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

    Publication Year: 2009 , Page(s): 127 - 138
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4492 KB) |  | HTML iconHTML  

    Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations. View full abstract»

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  • One of the Last Updates on Rambus Standardization Skullduggery

    Publication Year: 2009 , Page(s): 139 - 143
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    First Page of the Article
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  • System Green [review of Hot, Flat, and Crowded: Why We Need a Green Revolution and How It Can Renew America (Friedman, T.L.; 2008); 2008]

    Publication Year: 2009 , Page(s): 144 - 147
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  • [Back cover]

    Publication Year: 2009 , Page(s): c3
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  • [Back cover]

    Publication Year: 2009 , Page(s): c4
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Aims & Scope

High-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center