Scheduled System Maintenance
On Tuesday, September 26, IEEE Xplore will undergo scheduled maintenance from 1:00-4:00 PM ET.
During this time, there may be intermittent impact on performance. We apologize for any inconvenience.

# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 31

Publication Year: 2009, Page(s):C1 - C4
| PDF (52 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2009, Page(s): C2
| PDF (50 KB)
• ### Improving the Linearity of GaN HEMTs by Optimizing Epitaxial Structure

Publication Year: 2009, Page(s):361 - 364
Cited by:  Papers (7)  |  Patents (1)
| | PDF (596 KB) | HTML

This paper presents an effective method of improving the linearity of GaN/AlGaN high-electron mobility transistors (HEMTs) by optimizing barrier (AlGaN Layer) thickness or implementing doped GaN cap or a combination of both. HEMT devices with different epitaxial structures were simulated, fabricated, and measured to demonstrate this. Third-order intermodulation distortion and adjacent channel powe... View full abstract»

• ### Increase of Breakdown Voltage on AlGaN/GaN HEMTs by Employing Proton Implantation

Publication Year: 2009, Page(s):365 - 369
Cited by:  Papers (4)
| | PDF (483 KB) | HTML

The breakdown voltage of new AlGaN/GaN high electron mobility transistors (HEMTs) was increased considerably without sacrificing any other electrical characteristics by proton implantation. The breakdown voltage of proton-implanted AlGaN/GaN HEMTs with 150 KeV 1 times 1014 -cm-2 fluence after thermal annealing at 400 degC for 5 min under N2 ambient was 719 V, while... View full abstract»

• ### Low-Voltage Organic Field-Effect Transistor With PMMA/$hbox{ZrO}_{2}$ Bilayer Dielectric

Publication Year: 2009, Page(s):370 - 376
Cited by:  Papers (13)
| | PDF (870 KB) | HTML

This paper reports on the application of a bilayer polymethylmethacrylate (PMMA)/ZrO2 dielectric in copper ph-thalocyanine (CuPc) organic field-effect transistors (OFETs). By depositing a PMMA layer on ZrO2, the leakage of the dielectric is reduced by one order of magnitude compared to single- layer ZrO2. A high-quality interface is obtained between the organic sem... View full abstract»

• ### Designed Workfunction Engineering of Double-Stacked Metal Nanocrystals for Nonvolatile Memory Application

Publication Year: 2009, Page(s):377 - 382
Cited by:  Papers (18)
| | PDF (890 KB) | HTML

A double-stacked nanocrystal (DSNC) flash memory is presented for improvement of both program/erase (P/E) speed and data retention time. Four combinations of nickel (Ni) and gold (Au) (Ni/Ni, Au/Au, Ni/Au, and Au/Ni) are used as charge storage DSNC materials and are compared from the perspective of memory performance. Through experimental results for P/E efficiency and retention time, the optimize... View full abstract»

• ### Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits

Publication Year: 2009, Page(s):383 - 392
Cited by:  Papers (33)  |  Patents (2)
| | PDF (1390 KB) | HTML

This paper introduces the theory of a carbon-nanotube multichannel transistor and shows that, due to statistical averaging in such a structure, a lot of variations in growth and processing can be tolerated. A model of such a structure has been presented, and Monte Carlo simulations have been performed to identify which of the imperfections and sources of variation are more critical than others. We... View full abstract»

• ### A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

Publication Year: 2009, Page(s):393 - 398
Cited by:  Papers (50)  |  Patents (9)
| | PDF (714 KB) | HTML

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the c... View full abstract»

• ### Correlation of Charge Buildup and Stress-Induced Leakage Current in Cerium Oxide Films Grown on Ge (100) Substrates

Publication Year: 2009, Page(s):399 - 407
Cited by:  Papers (20)
| | PDF (292 KB) | HTML

High-kappa films are currently deposited on Ge substrates to compensate the mobility loss, as Ge offers higher mobility compared with that of silicon. This paper deals with the reliability characteristics of cerium oxide films grown by molecular beam deposition on n-type Ge (100) substrates. MOS capacitors with Pt gate electrodes were subjected to constant voltage stress conditions at accumulation... View full abstract»

• ### Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology

Publication Year: 2009, Page(s):408 - 419
Cited by:  Papers (33)
| | PDF (1399 KB) | HTML

A new fully experimental method to determine the backscattering coefficient and the ballistic ratio of n- and p-FDSOI and multigate nanodevices is proposed in this paper. This technique is the first one that takes multisubband population, carrier degeneracy, and short channel effects into account. Owing to self-consistent Poisson-Schrodinger simulations, common assumptions such as one subband occu... View full abstract»

• ### Experimental Investigation on the Quasi-Ballistic Transport: Part II—Backscattering Coefficient Extraction and Link With the Mobility

Publication Year: 2009, Page(s):420 - 430
Cited by:  Papers (27)
| | PDF (1192 KB) | HTML

Using a new extraction methodology taking into account multisubband population and carrier degeneracy, we have experimentally determined backscattering coefficients, ballistic ratios, and injection velocities of n- and p-FDSOI devices with gate lengths down to 30 nm in the saturated and, for the first time, in the linear regimes. The evolution of these quasi-ballistic parameters is examined as a f... View full abstract»

• ### Modeling and Parameter Extraction for the Series Resistance in Thin-Film Transistors

Publication Year: 2009, Page(s):431 - 440
Cited by:  Papers (20)
| | PDF (463 KB) | HTML

A new parameter extraction method is proposed for the series resistance of thin-film transistors (TFTs). By analyzing the gate-source overlap region of staggered structure TFTs, the model for the series resistance is derived and utilized for the parameter extraction. To verify the extraction method, the characteristics of amorphous silicon TFTs obtained from TCAD simulation are used. For the devic... View full abstract»

• ### High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

Publication Year: 2009, Page(s):441 - 447
Cited by:  Papers (3)
| | PDF (972 KB) | HTML

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device... View full abstract»

• ### A Novel Low-Cost Trigate Process Suitable for Embedded CMOS 1T-1C Pseudo-SRAM Application

Publication Year: 2009, Page(s):448 - 455
Cited by:  Papers (1)  |  Patents (1)
| | PDF (1443 KB) | HTML

A novel trigate process is described in this paper for low-cost embedded CMOS-based one transistor-one capacitor (1T-1C) pseudo-static-random-access-memory (pseudo-SRAM) applications. By utilizing hydrogen anneal and a selective hard mask on the capacitor, the pass transistor fin height can be reduced while keeping the capacitor height intact. This will allow us to maximize cell capacitance while ... View full abstract»

• ### Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

Publication Year: 2009, Page(s):456 - 465
Cited by:  Papers (113)  |  Patents (1)
| | PDF (1479 KB) | HTML

In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-b... View full abstract»

• ### Work Function Engineering Within a Single Metal Gate Stack: Manipulating Terbium- and Aluminum-Induced Interface Dipoles of Opposing Polarity

Publication Year: 2009, Page(s):466 - 473
Cited by:  Papers (2)
| | PDF (733 KB) | HTML

In this paper, a systematic study on combining n-type and p-type interface dipoles for metal gate work function (Phim) engineering within the same gate stack was conducted. Ultrathin terbium (Tb) and aluminum (Al)-based interlayers (ILs) were utilized for n- and p-type dipole formation, respectively, to modulate the net interface dipole magnitude and polarity within a metal gate stack. ... View full abstract»

• ### The Corbino Pseudo-MOSFET on SOI: Measurements, Model, and Applications

Publication Year: 2009, Page(s):474 - 482
Cited by:  Papers (11)
| | PDF (533 KB) | HTML

We propose the combination of magnetoresistance (MR) and Pseudo-MOSFET (Psi-MOSFET) measurements as an improved method for the characterization of silicon-on-insulator (SOI) materials. Measurements were performed on ultrathin SOI Psi-MOSFETs with Corbino geometry by applying high magnetic field and substrate biasing. Several models and extraction methods are developed and compared for an accurate ... View full abstract»

• ### Influence of Concurrent Electrothermal and Avalanche Effects on the Safe Operating Area of Multifinger Bipolar Transistors

Publication Year: 2009, Page(s):483 - 491
Cited by:  Papers (4)
| | PDF (581 KB) | HTML

The impact of the concurrent action of electrothermal and avalanche effects on the reduction of the safe operating area is experimentally investigated for a wide number of single-, two-, and three-finger bipolar transistors fabricated in SiGe, GaAs, and silicon-on-glass technologies. The results of the analysis are substantiated by a SPICE-like simulation tool that allows the monitoring of the tem... View full abstract»

• ### Physical Description of Quasi-Saturation and Impact-Ionization Effects in High-Voltage Drain-Extended MOSFETs

Publication Year: 2009, Page(s):492 - 498
Cited by:  Papers (14)
| | PDF (489 KB) | HTML

This paper presents a physical description of two specific aspects in drain-extended MOS transistors, i.e., quasi-saturation and impact-ionization effects. The 2-D device simulator Medici provides the physical insights, and both the unique features are originally attributed to the Kirk effect. The transistor dc model is derived from regional analysis of carrier transport in the intrinsic MOS and t... View full abstract»

• ### High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Publication Year: 2009, Page(s):499 - 504
Cited by:  Papers (17)  |  Patents (1)
| | PDF (811 KB) | HTML

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source-drain leakage. Here, we show that electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to five orders of magnitu... View full abstract»

• ### Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull

Publication Year: 2009, Page(s):505 - 511
Cited by:  Papers (4)
| | PDF (1082 KB) | HTML

Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous in... View full abstract»

• ### Comparison of Long-Wave Infrared Quantum-Dots-in-a-Well and Quantum-Well Focal Plane Arrays

Publication Year: 2009, Page(s):512 - 516
Cited by:  Papers (6)
| | PDF (544 KB) | HTML

This paper reports on a comparison between a commercially available quantum-well infrared focal plane array (FPA) and a custom quantum-dot (QD)-in-a-well (DWELL) infrared FPA in the long-wave infrared (LWIR). The DWELL detectors consist of an active region composed of InAs QDs embedded in In0.15Ga0.85As quantum wells. DWELL samples were grown using molecular beam epitaxy and ... View full abstract»

• ### Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

Publication Year: 2009, Page(s):517 - 522
Cited by:  Papers (19)
| | PDF (901 KB) | HTML

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the ... View full abstract»

• ### Extraction of Electron and Hole Ionization Coefficients From Metamorphically Grown InGaSb Diodes

Publication Year: 2009, Page(s):523 - 528
Cited by:  Papers (5)
| | PDF (534 KB) | HTML

Metamorphic pseudosubstrates of In0.15Ga0.85Sb are grown on p- and n-type GaSb substrates using InxGa1-xSb buffer layers compositionally graded in steps of x=0.03. Extensive material characterization was done on the metamorphic layers to determine the in-plane lattice constant, density of threading and misfit dislocations, and surface roughness by high-r... View full abstract»

• ### An Improvement to the Numerical Robustness of the Surface Potential Approximation for Double-Gate MOSFETs

Publication Year: 2009, Page(s):529 - 532
| | PDF (497 KB) | HTML

In developing the drain current model of a symmetric double-gate MOSFET, one encounters a transcendental equation relating the value of an intermediate variable beta to the gate and drain voltages. In this brief, we present an enhancement to an existing approximation for beta, which improves its numerical robustness. We also benchmark our suggested enhancement and show that our enhancement is as c... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy