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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 2 • Date Feb. 2009

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Displaying Results 1 - 24 of 24
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (39 KB)  
    Freely Available from IEEE
  • All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches

    Page(s): 285 - 293
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB) |  | HTML iconHTML  

    Time analog-to-digital converters (TADs) based on the power-supply voltage dependence of CMOS gate propagation delay time can be constructed solely of CMOS digital circuits and are characterized by output of the time integral of input voltage, with no dead time. This paper describes digital quadrature detection (DQD) by TAD (TAD-DQD). With TAD-DQD, the in-phase and quadrature components of the input signal, including amplitude and phase information, can be obtained simply by adding and subtracting AD-converted TAD output using a sampling frequency that is four times the carrier frequency of the target signal. As an example of the application of TAD-DQD, the standard-time and frequency-signal receiver circuits of a radio-controlled clock/watch are shown, and the experimental results demonstrate that the time code can in fact be received. View full abstract»

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  • Digital Background-Calibration Algorithm for “Split ADC” Architecture

    Page(s): 294 - 306
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB) |  | HTML iconHTML  

    The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms. View full abstract»

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  • Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver

    Page(s): 307 - 319
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB) |  | HTML iconHTML  

    In this paper, techniques to overcome the errors caused by the offset, gain, sample-time, and bandwidth mismatches among time-interleaved analog-to-digital converters in a high-speed baseband digital communication receiver are presented. The errors introduced by these mismatches are corrected using least-mean-square adaptation implemented in digital-signal-processing blocks. Gain, sample-time, and bandwidth mismatches are corrected by modifying the operation of the adaptive receive equalizer itself to minimize the hardware overhead. Simulation results show that the gain, offset, sample-time, and bandwidth mismatches are sufficiently corrected for practical digital communication receivers. View full abstract»

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  • A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

    Page(s): 320 - 326
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB) |  | HTML iconHTML  

    A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-mum CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of - 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm times 0.95 mm. View full abstract»

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  • Widely Programmable High-Frequency Active RC Filters in CMOS Technology

    Page(s): 327 - 336
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1072 KB) |  | HTML iconHTML  

    We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of ldquoconstant capacitance scalingrdquo is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 times range. The filter core, designed in a 0.18-mum CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB. View full abstract»

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  • A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids

    Page(s): 337 - 349
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1297 KB) |  | HTML iconHTML  

    We present a micropower digital modulator for class-D amplifiers for power-critical digital hearing aids. The modulator design embodies a proposed Lagrange interpolation (a combined first- and second-order Lagrange) algorithmic pulsewidth modulation (PWM) and a third-order DeltaSigma noise shaper. By means of double-Fourier-series analysis, we analyze and determine the harmonic nonlinearities of the proposed algorithmic PWM. At 48-kHz sampling, 96-kHz PWM output, 997-Hz input, and input modulation index=0.9, the modulator circuit achieves a total harmonic distortion+noise &nbsp;(<i>THD</i>+<i>N</i>) of - 74&nbsp;dB (0.02%) over an 8-kHz voice bandwidth-a 12-dB <i>THD</i>+<i>N</i> improvement over a reported design and yet dissipates only ~ 50% of the power. The proposed modulator dissipates the lowest power dissipation of all modulators compared, and by means of a proposed figure of merit, the proposed modulator exhibits very competitive performance. The modulator IC is fabricated in a 0.35-mum digital CMOS process with a core area of 0.46 mm<sup>2</sup>. View full abstract»

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  • Operation Limits for RTD-Based MOBILE Circuits

    Page(s): 350 - 363
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1490 KB) |  | HTML iconHTML  

    Resonant-tunneling-diode (RTD)-based monostable-bistable logic element (MOBILE) circuits operate properly in a certain frequency range. They exhibit both a minimum operating frequency and a maximum one. From a design point of view, it should be desirable to have gates with a correct operation from dc up to the maximum operating frequency (i.e., without the minimum bound). This paper undertakes this problem by analyzing how transistors and RTDs interact in RTD-based circuits. Two malfunctions have been identified: the incorrect evaluation of inputs and the lack of self-latching operation. The difficulty to study these problems in an analytical way has been overcome by resorting to series expansions for both the RTD and the heterojunction field-effect transistor I-V characteristics in the points of interest. We have obtained analytical expression linking representative device parameters and technological setup, for a MOBILE-based circuit to operate correctly. View full abstract»

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  • Digital Synthesizer/Mixer With Hybrid CORDIC–Multiplier Architecture: Error Analysis and Optimization

    Page(s): 364 - 373
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1178 KB) |  | HTML iconHTML  

    This paper describes a novel architecture for digital synthesizer/mixer (DSM). The operation performed by a DSM corresponds to a rotation of the input vector in the complex plane. The proposed architecture divides this rotation into three subrotations. The first one uses a few CORDIC stages, in which the rotation directions are in parallel computed with the help of a small lookup table. The CORDIC algorithm is employed also in the second subrotation, where the rotation directions are readily available after a simple recoding of the bits of the residual angle. The final rotation is multiplier based to reduce circuit latency and increase performances. A detailed error analysis and sizing methodology is given in this paper. It is shown that different versions of the architecture can be conceived by varying the dimensions of the second block and the topology of the third block. The proposed architecture exhibits very good performances, owing to the efficient carry-save implementation of CORDIC datapaths, the reduced lookup table, and the small size of multipliers. Implementations in a 0.25- mum CMOS technology are presented in order to demonstrate the design methodology and to investigate the implementation tradeoffs. View full abstract»

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  • Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers

    Page(s): 374 - 383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB) |  | HTML iconHTML  

    On-chip temperature gradient has emerged as a major design concern for high-performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. The main aim of this paper is to provide intelligent solution for minimizing the temperature-dependent clock skew by designing dynamically adaptive circuit elements, particularly the clock buffers. Using an RLC model of the clock tree, we investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles that can arise in practice due to different architectures and applications. As an effective way of mitigating the variable clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by up to 92.4%, leading to much improved clock synchronization and design performance. View full abstract»

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  • SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

    Page(s): 384 - 394
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (949 KB) |  | HTML iconHTML  

    In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in "many-core" SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to the elimination of power-hungry flip-flops and the efficient design of the source synchronization overhead. Moreover, eliminating the intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed, and solutions are put forward to alleviate it. Circuit simulations in a 65-nm process environment indicate that energy savings up to 20% are achievable for a six-cycle 9-mm-long 16-bit bus. View full abstract»

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  • Two-Dimensional Farrow Structure and the Design of Variable Fractional-Delay 2-D FIR Digital Filters

    Page(s): 395 - 404
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB) |  | HTML iconHTML  

    In this paper, a 2-D Farrow structure is proposed and used to implement variable fractional-delay (VFD) 2-D FIR digital filters. Compared with the existing literature, the desired response of a VFD 2-D digital filter is analyzed in detail, and it is found that there are four types of 2-D symmetric/antisymmetric sequences that need to be used for the design of VFD 2-D FIR digital filters. Moreover, due to the orthogonality among the approach functions, the four types of 2-D sequences can be determined independently, such that the dimension for each computation can be reduced drastically. For simplicity, only the designs of even-even- and odd-odd-order VFD 2-D filters are presented in this paper, and the other cases can be achieved in the same manner. To reveal the coefficient characteristics, the symmetric/antisymmetric properties of filter coefficients and the relationships between coefficients are all tabulated. Also, design examples such as nonseparable circularly symmetric low-pass VFD filters are presented to demonstrate the effectiveness of the proposed method. View full abstract»

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  • Low-Density Codes Based on Chaotic Systems for Simple Encoding

    Page(s): 405 - 415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    This paper proposes a new class of low-density generator-matrix codes (LDGM) based on chaotic dynamical systems. The codes are designed by controlling symbolic dynamics and using linear convolutional codes. Analyzing the complex structure of chaotic systems, iterative decoding is developed. The communication performance is studied, and convergence analysis of the iterative-decoding system is presented. Finally, comparison and advantages over LDGM linear block codes in terms of encoding complexity and bit-error-rate performance are described, and possible applications of our codes are discussed. View full abstract»

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  • Complex-Network Modeling of a Call Network

    Page(s): 416 - 429
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (891 KB) |  | HTML iconHTML  

    Recently, real-life data have revealed that the number of calls originating from or received by a telephone number in a network follows a power-law distribution. They show that a few telephone numbers make or receive a very large number of calls, whereas a large number of telephone numbers make or receive very few calls. The data have overthrown the general assumption that all telephone numbers are similar in generating telephone traffic. The first objective of this paper is to therefore construct a telephone call network (TCN) with connection properties following power-law distributions. With a more realistic TCN, researchers and engineers will be able to evaluate the telephone traffic behavior more accurately. Having constructed the aforementioned TCNs, we then consider the scenario when there is a sudden surge in the number of telephone calls, for example, during natural or man-made disasters. Under such a condition, the telephone network is usually overloaded and cannot operate properly. To mitigate the problem, we propose a preferential call blocking (PCB) scheme, aiming at blocking calls to target telephone numbers which have large numbers of incoming calls (in-strengths). We will investigate the effect on the carried traffic intensity when the PCB scheme is applied. We will compare the results with a benchmark, which corresponds to the case when all calls are blocked with equal probability. For the sake of completeness, we will also study the effectiveness of the blocking schemes when applied to a traditional TCN, in which all telephone numbers can call one another with equal probability. View full abstract»

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  • Synchronization of Passifiable Lurie Systems Via Limited-Capacity Communication Channel

    Page(s): 430 - 439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (826 KB) |  | HTML iconHTML  

    Output-feedback controlled synchronization problems for a class of nonlinear unstable systems under information constraints imposed by limited capacity of the communication channel are analyzed. A binary time-varying coder-decoder scheme is described, and a theoretical analysis for multidimensional master-slave systems represented in Lurie form (linear part plus nonlinearity depending only on measurable outputs) is provided. An output-feedback control law is proposed based on the passification theorem. It is shown that the synchronization error exponentially tends to zero for sufficiently high transmission rate (channel capacity). The results obtained for the synchronization problem can be extended to tracking problems in a straightforward manner if the reference signal is described by an external (exogenous) state space model. The results are illustrated by the controlled synchronization of two chaotic Chua systems via a communication channel with limited capacity. View full abstract»

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  • The Design and Analysis of a CMOS Low-Power Large-Neighborhood CNN With Propagating Connections

    Page(s): 440 - 452
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2317 KB) |  | HTML iconHTML  

    The design of a large-neighborhood cellular nonlinear network (LN-CNN) with propagating connections is proposed. The propagating connections are utilized to achieve large-neighborhood templates in the shape of diamonds. Based on the propagating connections, each LN-CNN cell can only be connected to neighboring cells without interconnections to farther cells. Thus, it is suitable for very large scale integration implementation. The LN-CNN functions of diffusion, deblurring, and Muller-Lyer illusion are successfully verified. Meanwhile, the functions of erosion and dilation are expanded with the diamond-shaped LN templates. Furthermore, the simple N- and P-type synapses stop all the static current paths so that the dc power dissipation can be reduced to only 0.7 mW on standby and 18 mW in operation. An experimental LN-CNN chip with a 20 &times; 20 array has been fabricated using 0.18-mum CMOS technology. With the proposed LN-CNN chip, more applications and LN-CNN templates can be studied further. View full abstract»

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  • Frequency Distortion of Second- and Third-Order Phase-Locked Loop Systems Using a Volterra-Series Approximation

    Page(s): 453 - 459
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (597 KB) |  | HTML iconHTML  

    In this paper, the frequency distortion for the nonlinear phase-locked loop (PLL) is derived analytically using a Volterra-series approximation. Both first- and second-order filters are considered in the PLL architecture. Theoretical results are then compared to those obtained via simulation. Comparisons are drawn between the two types of PLL with regard to the amount of distortion observed. Convergence of the Volterra-series solution is also discussed with regard to the system parameters. View full abstract»

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  • Systematic Methods for the Implementation of Nonlinear Wave-Digital Structures

    Page(s): 460 - 472
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB) |  | HTML iconHTML  

    Wave-digital (WD) structures containing adaptors with memory (characterized by port reflection filters) and nonlinear elements are suitable for the modeling of a wide range of nonlinear circuits and physical structures. In this paper, we propose two methods for automating the construction of algorithms that efficiently implement such structures, starting from their symbolic description. The former is based on the solution of state-space equations, while the latter is based on direct structural inspection. The state-space approach starts from the blockwise construction of a tableau matrix for the direct implementation of a generic WD structure and, for this reason, is here referred to as the wave tableau (WT) method. It has very general applicability as it works for a generic WD structure. The second technique (binary connection tree) implements a WD structure through a direct inspection (scanning) of the treelike topological representation of the reference model. Although valid for a slightly less general range of cases, this approach turns out to be much more efficient and flexible than that of the WT method. Such methods are particularly interesting for an interactive and immediate prototyping of physical models for the synthesis of sounds as they bring nonlinear WD structures with dynamic adaptors to a level of practical usability for a wide range of users while enabling the modeling of a wide variety of time-varying nonlinear physical models in an automatic fashion. The proposed solutions have been extensively tested on applications for the automatic modeling of acoustic interactions of musical interest. View full abstract»

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  • Nonconcurrent Error Correction in the Presence of Roundoff Noise

    Page(s): 473 - 484
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    This paper analyzes the effects of roundoff noise on our ability to nonconcurrently detect and identify transient faults that corrupt state variables during the operation of a fault-tolerant discrete-time linear time-invariant (LTI) dynamic system. Our analysis leads to two decoding algorithms, i.e., one based on the Peterson-Gorenstein-Zierler algorithm and the other based on singular-value decomposition techniques. We analytically obtain bounds on the roundoff noise level (equivalently, the precision) at which both algorithms can guarantee the correct determination of the number of errors. Our simulations verify our analysis and suggest that our bounds can be very tight for certain choices of design parameters. The developments in this paper can be used to provide guidance about the design of fault-tolerant systems and have immediate implications for digital implementations of LTI dynamic systems (e.g., digital filters) because such implementations unavoidably have to deal with finite-precision effects. View full abstract»

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  • A Power-Efficient Configurable Low-Complexity MIMO Detector

    Page(s): 485 - 496
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1468 KB) |  | HTML iconHTML  

    In this paper, we propose a power-efficient configurable multiple-input-multiple-output (MIMO) detector, supporting QPSK, 16-QAM, and 64-QAM with low complexity. The approach divides a large MIMO detector into two subsystems: a core detector and a residual detector. The core detector, a low-cost 2 times 2 V-BLAST with ML detector, is used to detect the first two significant outputs. This detector not only efficiently increases the reliability of the entire MIMO detector through its ML performance in mitigating error propagation but also reduces the computational complexity by its search space reduction capability to decrease the computation from O(C 2<) to O(C) (C is the constellation size). The residual detector is an ordered successive interference cancellation (OSIC) detector that detects the rest outputs. The results of bit-error-rate simulations demonstrate that the proposed detector significantly outperforms the OSIC detector. Furthermore, two complete ASIC implementations fabricated by 0.13- mu m 1P8M CMOS technology are presented. We show that the proposed detector, which is configurable from 2 times 2 to 6 times 4 MIMO configurations, has the lowest complexity compared to other fabricated works with 64-QAM demodulation. Moreover, the measured normalized power efficiency of 3.8 Mb/s/mW is shown to be the most power-efficient design compared with the designs of other fabricated works. View full abstract»

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  • Driving-Scheme Algorithms for Intelligent Energy-Efficient High-Voltage Display Drivers

    Page(s): 497 - 507
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    In this paper, different driving-scheme algorithms to reduce the energy consumption in bistable display drivers are presented. A thorough theoretical analysis as well as some results will be given. These results report the difference in energy consumption between drivers using the traditional driving schemes and drivers using the driving scheme presented in this paper and this for different image patterns. The proposed algorithms are suitable for bistable flat-panel displays like cholesteric liquid-crystal displays (LCDs), bistable nematic LCDs, or electrophoretic displays and are very important for battery-powered applications. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors

    Page(s): 508
    Save to Project icon | Request Permissions | PDF file iconPDF (41 KB)  
    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras