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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2009

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Displaying Results 1 - 25 of 36
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2009 , Page(s): C2
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  • Special Section on the International Symposium for Quality Electronic Design 2008 (ISQED 2008)

    Publication Year: 2009 , Page(s): 1 - 2
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  • Statistical Timing Models for Large Macro Cells and IP Blocks Considering Process Variations

    Publication Year: 2009 , Page(s): 3 - 11
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (669 KB) |  | HTML iconHTML  

    Integrated circuits today rely on extensive reuse of IP bocks and macro cells to meet the demand for high performance system-on-chip. We propose a methodology for extracting timing models of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in device and interconnect parameters. Increasing spatial correlations in variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a novel technique for instance-specific calibration of precharacterized timing model. The proposed approach was evaluated on large industrial designs of 1.2- and 3.5-M gates in 65-nm technology and validated against SPICE for accuracy. View full abstract»

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  • A Simplified Design Model for Random Process Variability

    Publication Year: 2009 , Page(s): 12 - 21
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB) |  | HTML iconHTML  

    A method for modeling the effects of random process variation through measured transistor current is introduced. The methodology culminates by modeling random current variation at a given operating point above threshold as a zero-mean Additive White Gaussian Noise (AWGN) current source with a standard deviation dependent on nominal operating current and design variables, the transistor sizes, W and L, and the transistor operating points, Vgs and Vds. The model has a simple posynomial form and is accurate compared to measured data within an RMS error of 5.4% for narrow-, wide-, short-, and long-channel transistors. The model's simplified form bridges the gap between existing statistical methods and circuit design. The efficacy of the model in the circuit design space will also be presented. In the analog domain, we will show that the contributions of this model can be used as a replacement for Monte Carlo methods for calculating circuit voltage and current variances. In the digital space, we will investigate the calculation of timing delay distributions. Results calculated via an alpha-power (¿p) law model for average current show that scaling the supply voltage by ¿ results in an approximately 1/¿¿p+1.1 scaling in the path-delay standard deviation for a 65-nm process. View full abstract»

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  • Root-Finding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations

    Publication Year: 2009 , Page(s): 22 - 30
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1154 KB) |  | HTML iconHTML  

    In this paper, we propose a closed-form method to evaluate the read stability of an SRAM cell via quartic root finding. By utilizing a simplified MOSFET device model, we model SRAM cell stability by a system of quartic equations. The algebraic nature of the equations along with simplified region boundaries provide the insight that only a few combinations of device operating regions correspond to the stability of the cell, instead of 729 combinations in the brute force approach. Such an insight not only makes it possible to have a quick ¿litmus test¿ to determine cell stability under variability but also significantly speeds up the analysis, compared to a traditional SPICE approach. Experimental results using industrial bulk CMOS models show that the results are in excellent agreement with SPICE results and 65× faster. View full abstract»

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  • Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

    Publication Year: 2009 , Page(s): 31 - 39
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1177 KB) |  | HTML iconHTML  

    The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%. View full abstract»

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  • Characterization of Standard Cells for Intra-Cell Mismatch Variations

    Publication Year: 2009 , Page(s): 40 - 49
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (757 KB) |  | HTML iconHTML  

    With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variation (referred to as statistical characterization). Statistical characterization needs to be performed efficiently with acceptable accuracy as a function of several process and environmental parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and nonswitching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvement with acceptable accuracy, compared with Monte Carlo simulation. We show that this approach ensures an upper bound on the results while keeping the number of simulations for each cell independent of the number of devices. View full abstract»

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  • Special Section on the 2008 International Conference on Microelectronic Test Structures

    Publication Year: 2009 , Page(s): 50
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  • Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

    Publication Year: 2009 , Page(s): 51 - 58
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1777 KB) |  | HTML iconHTML  

    A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs. View full abstract»

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  • Characterization of STI Edge Effects on CMOS Variability

    Publication Year: 2009 , Page(s): 59 - 65
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1521 KB) |  | HTML iconHTML  

    Layout effects (well proximity effect, gate-STI distance effect, litho proximity effects, etc.) can lead to significant deviations between measured and modeled drain currents in advanced CMOS processes. Because several of these effects can occur at the same time and because a proper distinction between systematic and random effects is not always made, this often leads to confusion on the subject of variability. Using a dedicated set of-asymmetrically designed-matched pair test structures and a data analysis technique based on so-called mismatch sweeps, we answer some important questions in these discussions on variability in advanced CMOS technologies. Taking the STI-induced stress effect as an example, we show that, although there can be a large systematic offset in drain current and threshold voltage due to this effect, there is no significant impact on random mismatch fluctuations. View full abstract»

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  • Technique for the Rapid Characterization of Parametric Distributions

    Publication Year: 2009 , Page(s): 66 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    We present a technique for fast characterization of the statistical mean and sigma of parametric variations. The technique uses a scan chain to sequentially cycle through a device array, creating a periodic waveform that can be directly measured using a multimeter. The dc and root-mean square values of the waveform directly give the mean and sigma of the parameter distribution. We show the technique is sufficiently general and can be applied to a wide range of characterization strategies. A VTH characterization array was implemented in a 65-nm bulk CMOS process where we compare traditional individual device measurements for calculating statistics with the direct mean and sigma measurement technique using the multimeter. View full abstract»

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  • Comparison of Measurement Techniques for Linewidth Metrology on Advanced Photomasks

    Publication Year: 2009 , Page(s): 72 - 79
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (895 KB) |  | HTML iconHTML  

    This paper compares electrical, optical, and atomic force microscope (AFM) measurements of critical dimension (CD) made on a chrome on quartz photomask. Test structures suitable for direct, on-mask electrical probing have been measured using the above three techniques. These include cross-bridge linewidth structures and pairs of Kelvin bridge resistors designed to investigate dimensional mismatch. Overall, the results show very good agreement between the electrical measurements and those made with a calibrated CD-AFM system, while the optical metrology system overestimates the measured width. The uncertainty in each of the measurements has been considered, and for the first time an attempt has been made to describe the levels and sources of uncertainty in the electrical measurement of CD on advanced binary photomasks. View full abstract»

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  • Long-Range Lateral Dopant Diffusion in Tungsten Silicide Layers

    Publication Year: 2009 , Page(s): 80 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1422 KB) |  | HTML iconHTML  

    Novel diode test structures have been manufactured to characterize long-range dopant diffusion in tungsten silicide layers. A tungsten silicide to p-type silicon contact has been characterized as a Schottky barrier rectifying contact with a silicide work function of 4.8 eV. Long-range diffusion of boron for an anneal at 900degC for 30 min has been shown to alter this contact to become ohmic. Long-range diffusion of phosphorus with a similar anneal alters the contact to become a bipolar n-p diode. Bipolar diode action is demonstrated experimentally for anneal schedules of 30 min at 900deg C, indicating long-range diffusion of phosphorus ( ~ 38 mum). SIMS analysis shows dopant redistribution is adversely affected by segregation to the silicide/oxide interface. The concept of conduit diffusion has been demonstrated experimentally for application in advanced bipolar transistor technology. View full abstract»

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  • Test Structure for Characterizing Low Voltage Coplanar EWOD System

    Publication Year: 2009 , Page(s): 88 - 95
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1249 KB) |  | HTML iconHTML  

    This paper presents test structures designed for studying the relationship between the operating voltage and different electrode configurations and areas for coplanar electrowetting on dielectrics (EWOD) devices. New test structures have been designed and fabricated using anodic Ta2O5 dielectric and thin aFP (amorphous Fluoropolymer CYTOP from Asahi Glass Co., Ltd.). These test structures have been used to characterize the contact angle change, which is between 114deg and 81deg with an applied voltage of less than 20 V. This demonstrates that by modifying the coplanar architecture, the operating voltage can be reduced by a factor of two, compared to previously reported coplanar EWOD structures. Droplet manipulation on a coplanar EWOD system with this new design has been successfully demonstrated, with a driving voltage of 15 V. View full abstract»

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  • Comb Capacitor Structures for On-Chip Physical Uncloneable Function

    Publication Year: 2009 , Page(s): 96 - 102
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1252 KB) |  | HTML iconHTML  

    Planar inter-digitated comb capacitor structures are an excellent tool for on-chip capacitance measurement and evaluation of properties of coating layers with varying composition. These comb structures are easily fabricated in a single step in the last metallization layer of a standard IC process. Capacitive coupling of these structures with a coating layer is modelled based on the electric field distribution to have a detailed understanding of contributing capacitance components. The coating composition is optimized to provide maximum spread in capacitance values of comb capacitor structures. This spread in measured capacitance values can be used to implement a physical uncloneable function (PUF). A PUF is a random function which can be evaluated only with the help of a physical system. We present an on-chip capacitive PUF for chip security and data storage in which the unlock key algorithm is generated from capacitors which are physically linked to the chip in an inseparable way. The strength of this key increases with the spread in capacitance values and measurement accuracy. View full abstract»

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  • Evaluation of Packaging-Induced Performance Change for Small-Scale Analog IC

    Publication Year: 2009 , Page(s): 103 - 109
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1488 KB) |  | HTML iconHTML  

    The impact of packaging-induced circuit performance changes for a small-scale integrated circuit (IC) smaller than 1.0 mm 2 has been evaluated by a new method with specially designed test chips. Analog circuits such as power management ICs for portable electronic devices are small-scale chips and require high-accuracy operation. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence, after which one distribution chart was reproduced from all of the measurement results. The present method enables the characteristic distribution on the chip surface to visualize not only the electrical parametric distribution but also the residual stress distribution, even though small-scale ICs have a limited number of bonding pads. In addition, a new method for evaluating the circuit performance change of an analog circuit due to stress-induced parametric changes is presented. View full abstract»

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  • Integrated Procedure Automating Test Chip Layout, Place and Route, and Test Plan Development for Efficient Parametric Device and Process Design

    Publication Year: 2009 , Page(s): 110 - 118
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2193 KB) |  | HTML iconHTML  

    This work describes a novel system for device development that automates and fully integrates the workflow from test chip construction, from placement and routing to electrical test program generation. In addition to accelerating test chip and test program development, this system facilitates parameterized data analysis, thereby providing a framework that finally allows the user to realize the full benefits of complex and elegant experimental device designs. By utilizing a centralized database and eliminating parameter re-entry, the automation provided by this integrated approach eliminates many of the sources for human error while maximizing reuse between technologies. View full abstract»

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  • Test Circuit for Measuring Pulse Widths of Single-Event Transients Causing Soft Errors

    Publication Year: 2009 , Page(s): 119 - 125
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1055 KB) |  | HTML iconHTML  

    A novel on-chip test circuit to measure single-event transient (SET) pulse widths has been developed and implemented in IBM 130-nm and 90-nm processes for characterizing logic soft errors. Test measurements with heavy ions and alpha particles show transient widths ranging from 100 ps to over 1 ns, comparable to legitimate logic signals in such technologies. Design options to limit the SET pulse width and hence to mitigate soft errors are evaluated with the test circuit to demonstrate the effectiveness of such design techniques. View full abstract»

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  • Characterization for High-Performance CMOS Using In-Wafer Advanced Kelvin-Contact Device Structure

    Publication Year: 2009 , Page(s): 126 - 133
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (811 KB) |  | HTML iconHTML  

    In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current-voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method. View full abstract»

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  • A Novel Biasing Technique for Addressable Parametric Arrays

    Publication Year: 2009 , Page(s): 134 - 145
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1749 KB) |  | HTML iconHTML  

    Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 times 32 and 4 times 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence. View full abstract»

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  • Cross-Bridge Kelvin Resistor Structures for Reliable Measurement of Low Contact Resistances and Contact Interface Characterization

    Publication Year: 2009 , Page(s): 146 - 152
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (927 KB) |  | HTML iconHTML  

    The parasitic factors that strongly influence the measurement accuracy of Cross-Bridge Kelvin Resistor (CBKR) structures for low specific contact resistances (¿c) have been extensively discussed during last few decades and the minimum of the ¿c value, which could be accurately extracted, was estimated. We fabricated a set of various metal-to-metal CBKR structures with different geometries, i.e., shapes and dimensions, to confirm this limit experimentally and to create a method for contact metal-to-metal interface characterization. As a result, a model was developed to account for the actual current flow and a method for reliable ¿c extraction was created. This method allowed to characterize metal-to-metal contact interface. It was found that in the case of ideal metal-to-metal contacts, the measured CBKR contact resistance was determined by the dimensions of the two-metal stack in the area of contact and sheet resistances of the metals used. View full abstract»

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  • Special Section on Supply Chain Management in the Semiconductor Industry

    Publication Year: 2009 , Page(s): 153
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    Freely Available from IEEE
  • Control-Relevant Demand Forecasting for Tactical Decision-Making in Semiconductor Manufacturing Supply Chain Management

    Publication Year: 2009 , Page(s): 154 - 163
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1580 KB) |  | HTML iconHTML  

    Forecasting highly uncertain demand signals is an important component for successfully managing inventory in semiconductor supply chains. We present a control-relevant approach to the problem that tailors a forecasting model to its end-use purpose, which is to provide forecast signals for a tactical inventory management policy based on model predictive control (MPC). The success of the method hinges on a control-relevant prefiltering operation applied to demand estimation data that emphasizes a goodness-of-fit in regions of time and frequency most important for achieving desired levels of closed-loop performance. A multiobjective formulation is presented that allows the supply-chain planner to generate demand forecasts that minimize inventory deviation, starts change variance, or their weighted combination when incorporated in an MPC decision policy. The benefits obtained from this procedure are demonstrated on a case study drawn from the final stage of a semiconductor manufacturing supply chain. View full abstract»

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  • Simulation of Semiconductor Manufacturing Supply-Chain Systems With DEVS, MPC, and KIB

    Publication Year: 2009 , Page(s): 164 - 174
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1283 KB) |  | HTML iconHTML  

    The dynamics of high-volume discrete-part semiconductor manufacturing supply-chain systems can be described using a combination of Discrete EVent System Specification (DEVS) and model predictive control (MPC) modeling approaches. To formulate the interactions between the discrete process model and its controller, another model called Knowledge Interchange Broker (KIB) is used. A robust and scalable testbed supporting DEVS-based manufacturing process modeling, MPC-based controller design, and the KIBDEVS/MPC interaction model is developed. A suite of experiments have been devised and simulated using this testbed. The flexibility of this approach for modeling, simulating, and evaluating stochastic discrete process models under alternative control schemes is detailed. The testbed illustrates the benefits and challenges associated with developing and using realistic manufacturing process models and process control policies. The simulation environment demonstrates the importance of explicitly defining and exposing the interactions between the manufacturing and control subsystems of complex semiconductor supply-chain systems. View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721